Lines Matching refs:nwl_bridge_writel
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() function
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); in nwl_pcie_misc_handler()
343 nwl_bridge_writel(pcie, 1 << bit, status_reg); in nwl_pcie_handle_msi_irq()
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); in nwl_mask_leg_irq()
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); in nwl_unmask_leg_irq()
587 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
591 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
596 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); in nwl_pcie_enable_msi()
597 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); in nwl_pcie_enable_msi()
603 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
605 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & in nwl_pcie_enable_msi()
608 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
614 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
616 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & in nwl_pcie_enable_msi()
619 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
638 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
640 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
644 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, in nwl_pcie_bridge_init()
648 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | in nwl_pcie_bridge_init()
652 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); in nwl_pcie_bridge_init()
655 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, in nwl_pcie_bridge_init()
660 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | in nwl_pcie_bridge_init()
674 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
681 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
683 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
715 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
718 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_bridge_init()
722 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
725 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
728 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_bridge_init()
732 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
735 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | in nwl_pcie_bridge_init()