pci/controller/pcie-xilinx-cpm.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * PCIe host controller driver for Xilinx Versal CPM DMA Bridge
5  * (C) Copyright 2019 - 2020, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
106 	CPM5,
110  * struct xilinx_cpm_variant - CPM variant information
118  * struct xilinx_cpm_pcie - PCIe port information
145 	return readl_relaxed(port->reg_base + reg);
151 	writel_relaxed(val, port->reg_base + reg);
165 		dev_dbg(port->dev, "Requester ID %lu\n",
179 	mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
180 	raw_spin_lock_irqsave(&port->lock, flags);
183 	raw_spin_unlock_irqrestore(&port->lock, flags);
193 	mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
194 	raw_spin_lock_irqsave(&port->lock, flags);
197 	raw_spin_unlock_irqrestore(&port->lock, flags);
207  * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
219 	irq_set_chip_data(irq, domain->host_data);
243 		generic_handle_domain_irq(port->intx_domain, i);
253 	raw_spin_lock(&port->lock);
255 	val &= ~BIT(d->hwirq);
257 	raw_spin_unlock(&port->lock);
265 	raw_spin_lock(&port->lock);
267 	val |= BIT(d->hwirq);
269 	raw_spin_unlock(&port->lock);
273 	.name		= "RC-Event",
283 	irq_set_chip_data(irq, domain->host_data);
303 		generic_handle_domain_irq(port->cpm_domain, i);
306 	if (port->variant->version == CPM5) {
307 		val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
309 			writel_relaxed(val, port->cpm_base +
317 	val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
320 			       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
356 	struct device *dev = port->dev;
359 	d = irq_domain_get_irq_data(port->cpm_domain, irq);
361 	switch (d->hwirq) {
369 		if (intr_cause[d->hwirq].str)
370 			dev_warn(dev, "%s\n", intr_cause[d->hwirq].str);
372 			dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq);
380 	if (port->intx_domain) {
381 		irq_domain_remove(port->intx_domain);
382 		port->intx_domain = NULL;
385 	if (port->cpm_domain) {
386 		irq_domain_remove(port->cpm_domain);
387 		port->cpm_domain = NULL;
392  * xilinx_cpm_pcie_init_irq_domain - Initialize IRQ domain
399 	struct device *dev = port->dev;
400 	struct device_node *node = dev->of_node;
407 		return -EINVAL;
410 	port->cpm_domain = irq_domain_add_linear(pcie_intc_node, 32,
413 	if (!port->cpm_domain)
416 	irq_domain_update_bus_token(port->cpm_domain, DOMAIN_BUS_NEXUS);
418 	port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
421 	if (!port->intx_domain)
424 	irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
427 	raw_spin_lock_init(&port->lock);
435 	return -ENOMEM;
440 	struct device *dev = port->dev;
444 	port->irq = platform_get_irq(pdev, 0);
445 	if (port->irq < 0)
446 		return port->irq;
454 		irq = irq_create_mapping(port->cpm_domain, i);
457 			return -ENXIO;
468 	port->intx_irq = irq_create_mapping(port->cpm_domain,
470 	if (!port->intx_irq) {
472 		return -ENXIO;
476 	irq_set_chained_handler_and_data(port->intx_irq,
480 	irq_set_chained_handler_and_data(port->irq,
487  * xilinx_cpm_pcie_init_port - Initialize hardware
493 		dev_info(port->dev, "PCIe Link is UP\n");
495 		dev_info(port->dev, "PCIe Link is DOWN\n");
511 	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
513 	if (port->variant->version == CPM5) {
515 		       port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
525  * xilinx_cpm_pcie_parse_dt - Parse Device tree
534 	struct device *dev = port->dev;
538 	port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
540 	if (IS_ERR(port->cpm_base))
541 		return PTR_ERR(port->cpm_base);
545 		return -ENXIO;
547 	port->cfg = pci_ecam_create(dev, res, bus_range,
549 	if (IS_ERR(port->cfg))
550 		return PTR_ERR(port->cfg);
552 	if (port->variant->version == CPM5) {
553 		port->reg_base = devm_platform_ioremap_resource_byname(pdev,
555 		if (IS_ERR(port->reg_base))
556 			return PTR_ERR(port->reg_base);
558 		port->reg_base = port->cfg->win;
566 	irq_set_chained_handler_and_data(port->intx_irq, NULL, NULL);
567 	irq_set_chained_handler_and_data(port->irq, NULL, NULL);
571  * xilinx_cpm_pcie_probe - Probe function
579 	struct device *dev = &pdev->dev;
586 		return -ENODEV;
590 	port->dev = dev;
596 	bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
598 		err = -ENODEV;
602 	port->variant = of_device_get_match_data(dev);
604 	err = xilinx_cpm_pcie_parse_dt(port, bus->res);
618 	bridge->sysdata = port->cfg;
619 	bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;
630 	pci_ecam_free(port->cfg);
641 	.version = CPM5,
646 		.compatible = "xlnx,versal-cpm-host-1.00",
650 		.compatible = "xlnx,versal-cpm5-host",
658 		.name = "xilinx-cpm-pcie",