Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
30 * dedicated outbound regions is mapped.
35 * dedicated outbound region.
37 * the MSI/legacy IRQ dedicated outbound region.
69 int num_pass_bits = fls64(pci_addr ^ (pci_addr + size - 1)); in rockchip_pcie_ep_ob_atu_num_bits()
86 addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | in rockchip_pcie_prog_ep_ob_atu()
107 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_write_header()
112 hdr->vendorid | hdr->subsys_vendor_id << 16, in rockchip_pcie_ep_write_header()
117 reg = (reg & 0xFFFF) | (hdr->deviceid << 16); in rockchip_pcie_ep_write_header()
121 hdr->revid | in rockchip_pcie_ep_write_header()
122 hdr->progif_code << 8 | in rockchip_pcie_ep_write_header()
123 hdr->subclass_code << 16 | in rockchip_pcie_ep_write_header()
124 hdr->baseclass_code << 24, in rockchip_pcie_ep_write_header()
126 rockchip_pcie_write(rockchip, hdr->cache_line_size, in rockchip_pcie_ep_write_header()
129 rockchip_pcie_write(rockchip, hdr->subsys_id << 16, in rockchip_pcie_ep_write_header()
132 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, in rockchip_pcie_ep_write_header()
143 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_set_bar()
144 dma_addr_t bar_phys = epf_bar->phys_addr; in rockchip_pcie_ep_set_bar()
145 enum pci_barno bar = epf_bar->barno; in rockchip_pcie_ep_set_bar()
146 int flags = epf_bar->flags; in rockchip_pcie_ep_set_bar()
151 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE); in rockchip_pcie_ep_set_bar()
157 sz = 1ULL << fls64(sz - 1); in rockchip_pcie_ep_set_bar()
158 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ in rockchip_pcie_ep_set_bar()
167 return -EINVAL; in rockchip_pcie_ep_set_bar()
186 b = bar - BAR_4; in rockchip_pcie_ep_set_bar()
211 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_clear_bar()
213 enum pci_barno bar = epf_bar->barno; in rockchip_pcie_ep_clear_bar()
220 b = bar - BAR_4; in rockchip_pcie_ep_clear_bar()
246 struct rockchip_pcie *pcie = &ep->rockchip; in rockchip_pcie_ep_map_addr()
251 set_bit(r, &ep->ob_region_map); in rockchip_pcie_ep_map_addr()
252 ep->ob_addr[r] = addr; in rockchip_pcie_ep_map_addr()
261 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_unmap_addr()
264 for (r = 0; r < ep->max_regions; r++) in rockchip_pcie_ep_unmap_addr()
265 if (ep->ob_addr[r] == addr) in rockchip_pcie_ep_unmap_addr()
268 if (r == ep->max_regions) in rockchip_pcie_ep_unmap_addr()
273 ep->ob_addr[r] = 0; in rockchip_pcie_ep_unmap_addr()
274 clear_bit(r, &ep->ob_region_map); in rockchip_pcie_ep_unmap_addr()
281 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_set_msi()
301 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_get_msi()
308 return -EINVAL; in rockchip_pcie_ep_get_msi()
317 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_assert_intx()
322 ep->irq_pending |= BIT(intx); in rockchip_pcie_ep_assert_intx()
328 ep->irq_pending &= ~BIT(intx); in rockchip_pcie_ep_assert_intx()
341 cmd = rockchip_pcie_read(&ep->rockchip, in rockchip_pcie_ep_send_legacy_irq()
346 return -EINVAL; in rockchip_pcie_ep_send_legacy_irq()
362 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_send_msi_irq()
369 flags = rockchip_pcie_read(&ep->rockchip, in rockchip_pcie_ep_send_msi_irq()
373 return -EINVAL; in rockchip_pcie_ep_send_msi_irq()
380 return -EINVAL; in rockchip_pcie_ep_send_msi_irq()
383 data_mask = msi_count - 1; in rockchip_pcie_ep_send_msi_irq()
388 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); in rockchip_pcie_ep_send_msi_irq()
401 /* Set the outbound region if needed. */ in rockchip_pcie_ep_send_msi_irq()
402 if (unlikely(ep->irq_pci_addr != (pci_addr & PCIE_ADDR_MASK) || in rockchip_pcie_ep_send_msi_irq()
403 ep->irq_pci_fn != fn)) { in rockchip_pcie_ep_send_msi_irq()
404 r = rockchip_ob_region(ep->irq_phys_addr); in rockchip_pcie_ep_send_msi_irq()
406 ep->irq_phys_addr, in rockchip_pcie_ep_send_msi_irq()
409 ep->irq_pci_addr = (pci_addr & PCIE_ADDR_MASK); in rockchip_pcie_ep_send_msi_irq()
410 ep->irq_pci_fn = fn; in rockchip_pcie_ep_send_msi_irq()
413 writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK)); in rockchip_pcie_ep_send_msi_irq()
429 return -EINVAL; in rockchip_pcie_ep_raise_irq()
436 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_start()
441 list_for_each_entry(epf, &epc->pci_epf, list) in rockchip_pcie_ep_start()
442 cfg |= BIT(epf->func_no); in rockchip_pcie_ep_start()
478 struct device *dev = rockchip->dev; in rockchip_pcie_parse_ep_dt()
489 err = of_property_read_u32(dev->of_node, in rockchip_pcie_parse_ep_dt()
490 "rockchip,max-outbound-regions", in rockchip_pcie_parse_ep_dt()
491 &ep->max_regions); in rockchip_pcie_parse_ep_dt()
492 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) in rockchip_pcie_parse_ep_dt()
493 ep->max_regions = MAX_REGION_LIMIT; in rockchip_pcie_parse_ep_dt()
495 ep->ob_region_map = 0; in rockchip_pcie_parse_ep_dt()
497 err = of_property_read_u8(dev->of_node, "max-functions", in rockchip_pcie_parse_ep_dt()
498 &ep->epc->max_functions); in rockchip_pcie_parse_ep_dt()
500 ep->epc->max_functions = 1; in rockchip_pcie_parse_ep_dt()
506 { .compatible = "rockchip,rk3399-pcie-ep"},
512 struct device *dev = &pdev->dev; in rockchip_pcie_ep_probe()
523 return -ENOMEM; in rockchip_pcie_ep_probe()
525 rockchip = &ep->rockchip; in rockchip_pcie_ep_probe()
526 rockchip->is_rc = false; in rockchip_pcie_ep_probe()
527 rockchip->dev = dev; in rockchip_pcie_ep_probe()
535 ep->epc = epc; in rockchip_pcie_ep_probe()
554 max_regions = ep->max_regions; in rockchip_pcie_ep_probe()
555 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr), in rockchip_pcie_ep_probe()
558 if (!ep->ob_addr) { in rockchip_pcie_ep_probe()
559 err = -ENOMEM; in rockchip_pcie_ep_probe()
566 windows = devm_kcalloc(dev, ep->max_regions, in rockchip_pcie_ep_probe()
569 err = -ENOMEM; in rockchip_pcie_ep_probe()
572 for (i = 0; i < ep->max_regions; i++) { in rockchip_pcie_ep_probe()
573 windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i); in rockchip_pcie_ep_probe()
577 err = pci_epc_multi_mem_init(epc, windows, ep->max_regions); in rockchip_pcie_ep_probe()
585 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, in rockchip_pcie_ep_probe()
587 if (!ep->irq_cpu_addr) { in rockchip_pcie_ep_probe()
589 err = -ENOMEM; in rockchip_pcie_ep_probe()
593 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; in rockchip_pcie_ep_probe()
596 * MSI-X is not supported but the controller still advertises the MSI-X in rockchip_pcie_ep_probe()
598 * allocating MSI-X vectors which cannot be used. Avoid this by skipping in rockchip_pcie_ep_probe()
599 * the MSI-X capability entry in the PCIe capabilities linked-list: get in rockchip_pcie_ep_probe()
600 * the next pointer from the MSI-X entry and set that in the MSI in rockchip_pcie_ep_probe()
601 * capability entry (which is the previous entry). This way the MSI-X in rockchip_pcie_ep_probe()
602 * entry is skipped (left out of the linked-list) and not advertised. in rockchip_pcie_ep_probe()
633 .name = "rockchip-pcie-ep",