Lines Matching full:pcie
3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
33 #include "pcie-rcar.h"
44 /* Structure representing the PCIe interface */
46 struct rcar_pcie pcie; member
71 * Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup()
72 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup()
98 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
101 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
123 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
130 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); in rcar_pci_write_reg_workaround()
132 rcar_pci_write_reg(pcie, val, reg); in rcar_pci_write_reg_workaround()
137 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, in rcar_pci_read_reg_workaround() argument
144 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); in rcar_pci_read_reg_workaround()
149 *val = rcar_pci_read_reg(pcie, reg); in rcar_pci_read_reg_workaround()
159 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
164 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); in rcar_pcie_config_access()
195 *data = rcar_pci_read_reg(pcie, PCICONF(index)); in rcar_pcie_config_access()
197 rcar_pci_write_reg(pcie, *data, PCICONF(index)); in rcar_pcie_config_access()
203 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); in rcar_pcie_config_access()
206 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | in rcar_pcie_config_access()
211 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR); in rcar_pcie_config_access()
213 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR); in rcar_pcie_config_access()
216 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) in rcar_pcie_config_access()
220 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & in rcar_pcie_config_access()
225 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); in rcar_pcie_config_access()
227 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); in rcar_pcie_config_access()
230 rcar_pci_write_reg(pcie, 0, PCIECCTLR); in rcar_pcie_config_access()
251 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", in rcar_pcie_read_conf()
271 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", in rcar_pcie_write_conf()
296 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) in rcar_pcie_force_speedup() argument
298 struct device *dev = pcie->dev; in rcar_pcie_force_speedup()
302 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) in rcar_pcie_force_speedup()
305 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { in rcar_pcie_force_speedup()
310 macsr = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_force_speedup()
315 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, in rcar_pcie_force_speedup()
319 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); in rcar_pcie_force_speedup()
323 rcar_pci_write_reg(pcie, macsr, MACSR); in rcar_pcie_force_speedup()
326 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); in rcar_pcie_force_speedup()
329 macsr = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_force_speedup()
332 rcar_pci_write_reg(pcie, macsr, MACSR); in rcar_pcie_force_speedup()
352 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_hw_enable() local
359 rcar_pcie_force_speedup(pcie); in rcar_pcie_hw_enable()
371 rcar_pcie_set_outbound(pcie, i, win); in rcar_pcie_hw_enable()
392 static int phy_wait_for_ack(struct rcar_pcie *pcie) in phy_wait_for_ack() argument
394 struct device *dev = pcie->dev; in phy_wait_for_ack()
398 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) in phy_wait_for_ack()
404 dev_err(dev, "Access to PCIe phy timed out\n"); in phy_wait_for_ack()
409 static void phy_write_reg(struct rcar_pcie *pcie, in phy_write_reg() argument
421 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); in phy_write_reg()
422 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); in phy_write_reg()
425 phy_wait_for_ack(pcie); in phy_write_reg()
428 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); in phy_write_reg()
429 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); in phy_write_reg()
432 phy_wait_for_ack(pcie); in phy_write_reg()
435 static int rcar_pcie_hw_init(struct rcar_pcie *pcie) in rcar_pcie_hw_init() argument
440 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_hw_init()
443 rcar_pci_write_reg(pcie, 1, PCIEMSR); in rcar_pcie_hw_init()
445 err = rcar_pcie_wait_for_phyrdy(pcie); in rcar_pcie_hw_init()
454 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); in rcar_pcie_hw_init()
460 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); in rcar_pcie_hw_init()
461 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); in rcar_pcie_hw_init()
464 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_hw_init()
465 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_hw_init()
467 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, in rcar_pcie_hw_init()
471 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, in rcar_pcie_hw_init()
475 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); in rcar_pcie_hw_init()
478 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); in rcar_pcie_hw_init()
481 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); in rcar_pcie_hw_init()
485 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); in rcar_pcie_hw_init()
487 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); in rcar_pcie_hw_init()
490 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); in rcar_pcie_hw_init()
493 err = rcar_pcie_wait_for_dl(pcie); in rcar_pcie_hw_init()
498 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); in rcar_pcie_hw_init()
507 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_phy_init_h1() local
510 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); in rcar_pcie_phy_init_h1()
511 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); in rcar_pcie_phy_init_h1()
512 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); in rcar_pcie_phy_init_h1()
513 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); in rcar_pcie_phy_init_h1()
514 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); in rcar_pcie_phy_init_h1()
515 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); in rcar_pcie_phy_init_h1()
516 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); in rcar_pcie_phy_init_h1()
517 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); in rcar_pcie_phy_init_h1()
518 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); in rcar_pcie_phy_init_h1()
519 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); in rcar_pcie_phy_init_h1()
520 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); in rcar_pcie_phy_init_h1()
521 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); in rcar_pcie_phy_init_h1()
523 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); in rcar_pcie_phy_init_h1()
524 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); in rcar_pcie_phy_init_h1()
525 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); in rcar_pcie_phy_init_h1()
532 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_phy_init_gen2() local
538 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); in rcar_pcie_phy_init_gen2()
539 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); in rcar_pcie_phy_init_gen2()
540 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
541 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
543 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); in rcar_pcie_phy_init_gen2()
545 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); in rcar_pcie_phy_init_gen2()
546 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
547 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); in rcar_pcie_phy_init_gen2()
570 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_msi_irq() local
572 struct device *dev = pcie->dev; in rcar_pcie_msi_irq()
575 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); in rcar_pcie_msi_irq()
589 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); in rcar_pcie_msi_irq()
593 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); in rcar_pcie_msi_irq()
617 .name = "PCIe MSI",
626 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_ack() local
629 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); in rcar_msi_irq_ack()
635 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_mask() local
640 value = rcar_pci_read_reg(pcie, PCIEMSIIER); in rcar_msi_irq_mask()
642 rcar_pci_write_reg(pcie, value, PCIEMSIIER); in rcar_msi_irq_mask()
649 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_msi_irq_unmask() local
654 value = rcar_pci_read_reg(pcie, PCIEMSIIER); in rcar_msi_irq_unmask()
656 rcar_pci_write_reg(pcie, value, PCIEMSIIER); in rcar_msi_irq_unmask()
668 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_compose_msi_msg() local
670 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; in rcar_compose_msi_msg()
671 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); in rcar_compose_msi_msg()
734 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; in rcar_allocate_domains() local
735 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); in rcar_allocate_domains()
741 dev_err(pcie->dev, "failed to create IRQ domain\n"); in rcar_allocate_domains()
748 dev_err(pcie->dev, "failed to create MSI domain\n"); in rcar_allocate_domains()
766 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_enable_msi() local
767 struct device *dev = pcie->dev; in rcar_pcie_enable_msi()
801 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); in rcar_pcie_enable_msi()
807 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); in rcar_pcie_enable_msi()
808 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); in rcar_pcie_enable_msi()
819 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_teardown_msi() local
822 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); in rcar_pcie_teardown_msi()
825 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); in rcar_pcie_teardown_msi()
832 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_get_resources() local
833 struct device *dev = pcie->dev; in rcar_pcie_get_resources()
837 host->phy = devm_phy_optional_get(dev, "pcie"); in rcar_pcie_get_resources()
845 pcie->base = devm_ioremap_resource(dev, &res); in rcar_pcie_get_resources()
846 if (IS_ERR(pcie->base)) in rcar_pcie_get_resources()
847 return PTR_ERR(pcie->base); in rcar_pcie_get_resources()
851 dev_err(dev, "cannot get pcie bus clock\n"); in rcar_pcie_get_resources()
879 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, in rcar_pcie_inbound_ranges() argument
897 dev_err(pcie->dev, "Failed to map inbound regions!\n"); in rcar_pcie_inbound_ranges()
917 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, in rcar_pcie_inbound_ranges()
936 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); in rcar_pcie_parse_map_dma_ranges()
945 { .compatible = "renesas,pcie-r8a7779",
947 { .compatible = "renesas,pcie-r8a7790",
949 { .compatible = "renesas,pcie-r8a7791",
951 { .compatible = "renesas,pcie-rcar-gen2",
953 { .compatible = "renesas,pcie-r8a7795",
955 { .compatible = "renesas,pcie-rcar-gen3",
964 struct rcar_pcie *pcie; in rcar_pcie_probe() local
974 pcie = &host->pcie; in rcar_pcie_probe()
975 pcie->dev = dev; in rcar_pcie_probe()
978 pm_runtime_enable(pcie->dev); in rcar_pcie_probe()
979 err = pm_runtime_get_sync(pcie->dev); in rcar_pcie_probe()
981 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); in rcar_pcie_probe()
1004 dev_err(dev, "failed to init PCIe PHY\n"); in rcar_pcie_probe()
1009 if (rcar_pcie_hw_init(pcie)) { in rcar_pcie_probe()
1010 dev_info(dev, "PCIe link down\n"); in rcar_pcie_probe()
1015 data = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_probe()
1016 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); in rcar_pcie_probe()
1061 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_resume() local
1072 dev_info(dev, "PCIe link down\n"); in rcar_pcie_resume()
1076 data = rcar_pci_read_reg(pcie, MACSR); in rcar_pcie_resume()
1077 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); in rcar_pcie_resume()
1085 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); in rcar_pcie_resume()
1086 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); in rcar_pcie_resume()
1089 rcar_pci_write_reg(pcie, val, PCIEMSIIER); in rcar_pcie_resume()
1100 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_resume_noirq() local
1102 if (rcar_pci_read_reg(pcie, PMSR) && in rcar_pcie_resume_noirq()
1103 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) in rcar_pcie_resume_noirq()
1106 /* Re-establish the PCIe link */ in rcar_pcie_resume_noirq()
1107 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); in rcar_pcie_resume_noirq()
1108 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); in rcar_pcie_resume_noirq()
1109 return rcar_pcie_wait_for_dl(pcie); in rcar_pcie_resume_noirq()
1119 .name = "rcar-pcie",
1135 { .compatible = "renesas,pcie-r8a7779" },
1136 { .compatible = "renesas,pcie-r8a7790" },
1137 { .compatible = "renesas,pcie-r8a7791" },
1138 { .compatible = "renesas,pcie-rcar-gen2" },