Lines Matching +full:bcm2711 +full:- +full:pcie
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
40 /* Broadcom STB PCIe Register Offsets */
147 /* PCIe parameters */
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
215 BCM2711,
221 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
222 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
248 /* Internal PCIe Host Controller Information.*/
265 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
266 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
271 static inline bool is_bmips(const struct brcm_pcie *pcie)
273 return pcie->type == BCM7435 || pcie->type == BCM7425;
278 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
286 return (log2_in - 12) + 0x1c;
289 return log2_in - 15;
342 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
348 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
353 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
360 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
366 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
374 return ssc && pll ? 0 : -EIO;
378 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
380 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
381 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
384 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
387 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
390 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
400 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
401 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
405 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
407 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
412 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
414 if (is_bmips(pcie))
422 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
425 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
428 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
431 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
435 .name = "BRCM STB PCIe MSI",
457 dev = msi->dev;
459 status = readl(msi->intr_base + MSI_INT_STATUS);
460 status >>= msi->legacy_shift;
462 for_each_set_bit(bit, &status, msi->nr) {
464 ret = generic_handle_domain_irq(msi->inner_domain, bit);
476 msg->address_lo = lower_32_bits(msi->target_addr);
477 msg->address_hi = upper_32_bits(msi->target_addr);
478 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
484 return -EINVAL;
490 const int shift_amt = data->hwirq + msi->legacy_shift;
492 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
507 mutex_lock(&msi->lock);
508 hwirq = bitmap_find_free_region(msi->used, msi->nr,
510 mutex_unlock(&msi->lock);
518 mutex_lock(&msi->lock);
519 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs));
520 mutex_unlock(&msi->lock);
526 struct brcm_msi *msi = domain->host_data;
536 &brcm_msi_bottom_irq_chip, domain->host_data,
547 brcm_msi_free(msi, d->hwirq, nr_irqs);
557 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
558 struct device *dev = msi->dev;
560 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
561 if (!msi->inner_domain) {
563 return -ENOMEM;
566 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
568 msi->inner_domain);
569 if (!msi->msi_domain) {
571 irq_domain_remove(msi->inner_domain);
572 return -ENOMEM;
580 irq_domain_remove(msi->msi_domain);
581 irq_domain_remove(msi->inner_domain);
584 static void brcm_msi_remove(struct brcm_pcie *pcie)
586 struct brcm_msi *msi = pcie->msi;
590 irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
596 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK :
599 writel(val, msi->intr_base + MSI_INT_MASK_CLR);
600 writel(val, msi->intr_base + MSI_INT_CLR);
606 writel(lower_32_bits(msi->target_addr) | 0x1,
607 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
608 writel(upper_32_bits(msi->target_addr),
609 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
611 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
612 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
615 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
619 struct device *dev = pcie->dev;
621 irq = irq_of_parse_and_map(dev->of_node, 1);
624 return -ENODEV;
629 return -ENOMEM;
631 mutex_init(&msi->lock);
632 msi->dev = dev;
633 msi->base = pcie->base;
634 msi->np = pcie->np;
635 msi->target_addr = pcie->msi_target_addr;
636 msi->irq = irq;
637 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
645 if (msi->legacy) {
646 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
647 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
648 msi->legacy_shift = 24;
650 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
651 msi->nr = BRCM_INT_PCI_MSI_NR;
652 msi->legacy_shift = 0;
659 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
662 pcie->msi = msi;
668 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
670 void __iomem *base = pcie->base;
676 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
678 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
688 struct brcm_pcie *pcie = bus->sysdata;
689 void __iomem *base = pcie->base;
696 /* An access to our HW w/o link-up will cause a CPU Abort */
697 if (!brcm_pcie_link_up(pcie))
701 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
702 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
709 struct brcm_pcie *pcie = bus->sysdata;
710 void __iomem *base = pcie->base;
717 /* An access to our HW w/o link-up will cause a CPU Abort */
718 if (!brcm_pcie_link_up(pcie))
722 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where);
723 writel(idx, base + IDX_ADDR(pcie));
724 return base + DATA_ADDR(pcie);
727 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
732 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
734 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
737 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
742 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
744 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
747 static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
749 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
753 reset_control_assert(pcie->perst_reset);
755 reset_control_deassert(pcie->perst_reset);
758 static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
763 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
765 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
768 static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
772 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
774 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
777 static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
781 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
783 struct device *dev = pcie->dev;
788 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
789 u64 pcie_beg = entry->res->start - entry->offset;
791 size += entry->res->end - entry->res->start + 1;
797 dev_err(dev, "DT node has no dma-ranges\n");
798 return -EINVAL;
801 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
806 pcie->num_memc = 1;
807 pcie->memc_size[0] = 1ULL << fls64(size - 1);
809 pcie->num_memc = ret;
813 for (i = 0, size = 0; i < pcie->num_memc; i++)
814 size += pcie->memc_size[i];
816 /* System memory starts at this address in PCIe-space */
819 *rc_bar2_size = 1ULL << fls64(size - 1);
823 * whatever the device-tree provides. This is because of an HW issue on
824 * early Raspberry Pi 4's revisions (bcm2711). It turns out its
825 * firmware has to dynamically edit dma-ranges due to a bug on the
826 * PCIe controller integration, which prohibits any access above the
827 * lower 3GB of memory. Given this, we decided to keep the dma-ranges
828 * in check, avoiding hard to debug device-tree related issues in the
831 * The PCIe host controller by design must set the inbound viewport to
834 * matters, the viewport must start on a pcie-address that is aligned
836 * represent system memory -- e.g. 3GB of memory requires a 4GB
837 * viewport -- we can map the outbound memory in or after 3GB and even
844 * - The best-case scenario, memory up to 3GB, is to place the inbound
845 * region in the first 4GB of pcie-space, as some legacy devices can
849 * - If the system memory is 4GB or larger we cannot start the inbound
854 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
858 return -EINVAL;
864 static int brcm_pcie_setup(struct brcm_pcie *pcie)
867 void __iomem *base = pcie->base;
875 pcie->bridge_sw_init_set(pcie, 1);
878 if (pcie->type == BCM2711)
879 pcie->perst_set(pcie, 1);
884 pcie->bridge_sw_init_set(pcie, 0);
887 if (is_bmips(pcie))
900 if (is_bmips(pcie))
902 else if (pcie->type == BCM2711)
904 else if (pcie->type == BCM7278)
921 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
934 for (memc = 0; memc < pcie->num_memc; memc++) {
935 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
951 * account the rounding-up we're forced to perform).
954 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
956 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
958 if (!brcm_pcie_rc_mode(pcie)) {
959 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
960 return -EINVAL;
963 /* disable the PCIe->GISB memory window (RC_BAR1) */
968 /* disable the PCIe->SCB memory window (RC_BAR3) */
973 /* Don't advertise L0s capability if 'aspm-no-l0s' */
975 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
984 * a PCIe-PCIe bridge (the default setting is to be EP mode).
991 bridge = pci_host_bridge_from_priv(pcie);
992 resource_list_for_each_entry(entry, &bridge->windows) {
993 struct resource *res = entry->res;
999 dev_err(pcie->dev, "too many outbound wins\n");
1000 return -EINVAL;
1003 if (is_bmips(pcie)) {
1004 u64 start = res->start;
1007 /* bmips PCIe outbound windows have a 128MB max size */
1011 brcm_pcie_set_outbound_win(pcie, j, start,
1012 start - entry->offset,
1016 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
1017 res->start - entry->offset,
1022 /* PCIe->SCB endian mode for BAR */
1031 static int brcm_pcie_start_link(struct brcm_pcie *pcie)
1033 struct device *dev = pcie->dev;
1034 void __iomem *base = pcie->base;
1041 pcie->perst_set(pcie, 0);
1044 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification
1045 * sections 2.2, PCIe r5.0, 6.6.1.
1051 * configure RC. Intermittently check status for link-up, up to a
1054 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
1057 if (!brcm_pcie_link_up(pcie)) {
1059 return -ENODEV;
1062 if (pcie->gen)
1063 brcm_pcie_set_gen(pcie, pcie->gen);
1065 if (pcie->ssc) {
1066 ret = brcm_pcie_set_ssc(pcie);
1106 sr->num_supplies = ARRAY_SIZE(supplies);
1108 sr->supplies[i].supply = supplies[i];
1116 struct brcm_pcie *pcie = bus->sysdata;
1117 struct device *dev = &bus->dev;
1121 if (!bus->parent || !pci_is_root_bus(bus->parent))
1124 if (dev->of_node) {
1131 pcie->sr = sr;
1133 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
1136 pcie->sr = NULL;
1140 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
1143 regulator_bulk_free(sr->num_supplies, sr->supplies);
1144 pcie->sr = NULL;
1149 brcm_pcie_start_link(pcie);
1155 struct brcm_pcie *pcie = bus->sysdata;
1156 struct subdev_regulators *sr = pcie->sr;
1157 struct device *dev = &bus->dev;
1159 if (!sr || !bus->parent || !pci_is_root_bus(bus->parent))
1162 if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
1164 regulator_bulk_free(sr->num_supplies, sr->supplies);
1165 pcie->sr = NULL;
1168 /* L23 is a low-power PCIe link state */
1169 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1171 void __iomem *base = pcie->base;
1191 dev_err(pcie->dev, "failed to enter low-power link state\n");
1194 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1204 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
1205 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
1208 void __iomem *base = pcie->base;
1211 for (i = beg; i != end; start ? i++ : i--) {
1223 ret = (tmp & combined_mask) == val ? 0 : -EIO;
1225 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1230 static inline int brcm_phy_start(struct brcm_pcie *pcie)
1232 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1235 static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1237 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1240 static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1242 void __iomem *base = pcie->base;
1245 if (brcm_pcie_link_up(pcie))
1246 brcm_pcie_enter_l23(pcie);
1248 pcie->perst_set(pcie, 1);
1260 /* Shutdown PCIe bridge */
1261 pcie->bridge_sw_init_set(pcie, 1);
1268 if (device_may_wakeup(&dev->dev)) {
1270 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n");
1277 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1278 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1281 brcm_pcie_turn_off(pcie);
1287 if (brcm_phy_stop(pcie))
1290 ret = reset_control_rearm(pcie->rescal);
1296 if (pcie->sr) {
1299 * downstream device is enabled as a wake-up source, do not
1302 pcie->ep_wakeup_capable = false;
1303 pci_walk_bus(bridge->bus, pci_dev_may_wakeup,
1304 &pcie->ep_wakeup_capable);
1305 if (!pcie->ep_wakeup_capable) {
1306 ret = regulator_bulk_disable(pcie->sr->num_supplies,
1307 pcie->sr->supplies);
1310 reset_control_reset(pcie->rescal);
1315 clk_disable_unprepare(pcie->clk);
1322 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1327 base = pcie->base;
1328 ret = clk_prepare_enable(pcie->clk);
1332 ret = reset_control_reset(pcie->rescal);
1336 ret = brcm_phy_start(pcie);
1341 pcie->bridge_sw_init_set(pcie, 0);
1351 ret = brcm_pcie_setup(pcie);
1355 if (pcie->sr) {
1356 if (pcie->ep_wakeup_capable) {
1363 pcie->ep_wakeup_capable = false;
1365 ret = regulator_bulk_enable(pcie->sr->num_supplies,
1366 pcie->sr->supplies);
1374 ret = brcm_pcie_start_link(pcie);
1378 if (pcie->msi)
1379 brcm_msi_set_regs(pcie->msi);
1384 if (pcie->sr)
1385 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
1387 reset_control_rearm(pcie->rescal);
1389 clk_disable_unprepare(pcie->clk);
1393 static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1395 brcm_msi_remove(pcie);
1396 brcm_pcie_turn_off(pcie);
1397 if (brcm_phy_stop(pcie))
1398 dev_err(pcie->dev, "Could not stop phy\n");
1399 if (reset_control_rearm(pcie->rescal))
1400 dev_err(pcie->dev, "Could not rearm rescal reset\n");
1401 clk_disable_unprepare(pcie->clk);
1406 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1407 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1409 pci_stop_root_bus(bridge->bus);
1410 pci_remove_root_bus(bridge->bus);
1411 __brcm_pcie_remove(pcie);
1469 .type = BCM2711,
1475 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1476 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1477 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1478 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1479 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1480 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1481 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1482 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1504 struct device_node *np = pdev->dev.of_node, *msi_np;
1507 struct brcm_pcie *pcie;
1510 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1512 return -ENOMEM;
1514 data = of_device_get_match_data(&pdev->dev);
1517 return -EINVAL;
1520 pcie = pci_host_bridge_priv(bridge);
1521 pcie->dev = &pdev->dev;
1522 pcie->np = np;
1523 pcie->reg_offsets = data->offsets;
1524 pcie->type = data->type;
1525 pcie->perst_set = data->perst_set;
1526 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1528 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1529 if (IS_ERR(pcie->base))
1530 return PTR_ERR(pcie->base);
1532 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1533 if (IS_ERR(pcie->clk))
1534 return PTR_ERR(pcie->clk);
1537 pcie->gen = (ret < 0) ? 0 : ret;
1539 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1541 ret = clk_prepare_enable(pcie->clk);
1543 dev_err(&pdev->dev, "could not enable clock\n");
1546 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1547 if (IS_ERR(pcie->rescal)) {
1548 clk_disable_unprepare(pcie->clk);
1549 return PTR_ERR(pcie->rescal);
1551 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1552 if (IS_ERR(pcie->perst_reset)) {
1553 clk_disable_unprepare(pcie->clk);
1554 return PTR_ERR(pcie->perst_reset);
1557 ret = reset_control_reset(pcie->rescal);
1559 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
1561 ret = brcm_phy_start(pcie);
1563 reset_control_rearm(pcie->rescal);
1564 clk_disable_unprepare(pcie->clk);
1568 ret = brcm_pcie_setup(pcie);
1572 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1573 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1574 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1575 ret = -ENODEV;
1579 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1580 if (pci_msi_enabled() && msi_np == pcie->np) {
1581 ret = brcm_pcie_enable_msi(pcie);
1583 dev_err(pcie->dev, "probe of internal MSI failed");
1588 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
1589 bridge->sysdata = pcie;
1591 platform_set_drvdata(pdev, pcie);
1594 if (!ret && !brcm_pcie_link_up(pcie))
1595 ret = -ENODEV;
1605 __brcm_pcie_remove(pcie);
1620 .name = "brcm-pcie",
1628 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");