Lines Matching +full:bus +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
19 #include <linux/pci-acpi.h>
20 #include <linux/pci-ecam.h>
74 return readl(port->csr_base + reg); in xgene_pcie_readl()
79 writel(val, port->csr_base + reg); in xgene_pcie_writel()
87 static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus) in pcie_bus_to_port() argument
92 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
94 cfg = bus->sysdata; in pcie_bus_to_port()
95 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
102 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) in xgene_pcie_get_cfg_base() argument
104 struct xgene_pcie *port = pcie_bus_to_port(bus); in xgene_pcie_get_cfg_base()
106 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
107 return port->cfg_base + AXI_EP_CFG_ACCESS; in xgene_pcie_get_cfg_base()
109 return port->cfg_base; in xgene_pcie_get_cfg_base()
113 * For Configuration request, RTDID register is used as Bus Number,
116 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) in xgene_pcie_set_rtdid_reg() argument
118 struct xgene_pcie *port = pcie_bus_to_port(bus); in xgene_pcie_set_rtdid_reg()
122 b = bus->number; in xgene_pcie_set_rtdid_reg()
126 if (!pci_is_root_bus(bus)) in xgene_pcie_set_rtdid_reg()
135 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
136 * the translation from PCI bus to native BUS. Entire DDR region
142 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) in xgene_pcie_hide_rc_bars() argument
144 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || in xgene_pcie_hide_rc_bars()
151 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, in xgene_pcie_map_bus() argument
154 if ((pci_is_root_bus(bus) && devfn != 0) || in xgene_pcie_map_bus()
155 xgene_pcie_hide_rc_bars(bus, offset)) in xgene_pcie_map_bus()
158 xgene_pcie_set_rtdid_reg(bus, devfn); in xgene_pcie_map_bus()
159 return xgene_pcie_get_cfg_base(bus) + offset; in xgene_pcie_map_bus()
162 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, in xgene_pcie_config_read32() argument
165 struct xgene_pcie *port = pcie_bus_to_port(bus); in xgene_pcie_config_read32()
167 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != in xgene_pcie_config_read32()
174 * we read the Vendor and Device ID of a non-existent device, the in xgene_pcie_config_read32()
181 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && in xgene_pcie_config_read32()
186 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in xgene_pcie_config_read32()
196 struct device *dev = &adev->dev; in xgene_get_csr_resource()
215 return -EINVAL; in xgene_get_csr_resource()
219 *res = *entry->res; in xgene_get_csr_resource()
226 struct device *dev = cfg->parent; in xgene_pcie_ecam_init()
234 return -ENOMEM; in xgene_pcie_ecam_init()
241 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); in xgene_pcie_ecam_init()
242 if (IS_ERR(port->csr_base)) in xgene_pcie_ecam_init()
243 return PTR_ERR(port->csr_base); in xgene_pcie_ecam_init()
245 port->cfg_base = cfg->win; in xgene_pcie_ecam_init()
246 port->version = ipversion; in xgene_pcie_ecam_init()
248 cfg->priv = port; in xgene_pcie_ecam_init()
285 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; in xgene_pcie_set_ib_mask()
313 port->link_up = false; in xgene_pcie_linkup()
316 port->link_up = true; in xgene_pcie_linkup()
325 struct device *dev = port->dev; in xgene_pcie_init_port()
328 port->clk = clk_get(dev, NULL); in xgene_pcie_init_port()
329 if (IS_ERR(port->clk)) { in xgene_pcie_init_port()
331 return -ENODEV; in xgene_pcie_init_port()
334 rc = clk_prepare_enable(port->clk); in xgene_pcie_init_port()
346 struct device *dev = port->dev; in xgene_pcie_map_reg()
350 port->csr_base = devm_pci_remap_cfg_resource(dev, res); in xgene_pcie_map_reg()
351 if (IS_ERR(port->csr_base)) in xgene_pcie_map_reg()
352 return PTR_ERR(port->csr_base); in xgene_pcie_map_reg()
355 port->cfg_base = devm_ioremap_resource(dev, res); in xgene_pcie_map_reg()
356 if (IS_ERR(port->cfg_base)) in xgene_pcie_map_reg()
357 return PTR_ERR(port->cfg_base); in xgene_pcie_map_reg()
358 port->cfg_addr = res->start; in xgene_pcie_map_reg()
367 struct device *dev = port->dev; in xgene_pcie_setup_ob_reg()
382 mask = ~(size - 1) | flag; in xgene_pcie_setup_ob_reg()
397 u64 addr = port->cfg_addr; in xgene_pcie_setup_cfg_reg()
408 struct device *dev = port->dev; in xgene_pcie_map_ranges()
410 resource_list_for_each_entry(window, &bridge->windows) { in xgene_pcie_map_ranges()
411 struct resource *res = window->res; in xgene_pcie_map_ranges()
419 pci_pio_to_address(res->start), in xgene_pcie_map_ranges()
420 res->start - window->offset); in xgene_pcie_map_ranges()
423 if (res->flags & IORESOURCE_PREFETCH) in xgene_pcie_map_ranges()
425 res->start, in xgene_pcie_map_ranges()
426 res->start - in xgene_pcie_map_ranges()
427 window->offset); in xgene_pcie_map_ranges()
430 res->start, in xgene_pcie_map_ranges()
431 res->start - in xgene_pcie_map_ranges()
432 window->offset); in xgene_pcie_map_ranges()
438 return -EINVAL; in xgene_pcie_map_ranges()
456 * X-Gene PCIe support maximum 3 inbound memory regions
476 return -EINVAL; in xgene_pcie_select_ib_reg()
480 struct of_pci_range *range, u8 *ib_reg_mask) in xgene_pcie_setup_ib_reg() argument
482 void __iomem *cfg_base = port->cfg_base; in xgene_pcie_setup_ib_reg()
483 struct device *dev = port->dev; in xgene_pcie_setup_ib_reg()
486 u64 cpu_addr = range->cpu_addr; in xgene_pcie_setup_ib_reg()
487 u64 pci_addr = range->pci_addr; in xgene_pcie_setup_ib_reg()
488 u64 size = range->size; in xgene_pcie_setup_ib_reg()
489 u64 mask = ~(size - 1) | EN_REG; in xgene_pcie_setup_ib_reg()
494 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); in xgene_pcie_setup_ib_reg()
496 dev_warn(dev, "invalid pcie dma-range config\n"); in xgene_pcie_setup_ib_reg()
500 if (range->flags & IORESOURCE_PREFETCH) in xgene_pcie_setup_ib_reg()
526 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); in xgene_pcie_setup_ib_reg()
531 struct device_node *np = port->node; in xgene_pcie_parse_map_dma_ranges()
532 struct of_pci_range range; in xgene_pcie_parse_map_dma_ranges() local
534 struct device *dev = port->dev; in xgene_pcie_parse_map_dma_ranges()
538 dev_err(dev, "missing dma-ranges property\n"); in xgene_pcie_parse_map_dma_ranges()
539 return -EINVAL; in xgene_pcie_parse_map_dma_ranges()
542 /* Get the dma-ranges from DT */ in xgene_pcie_parse_map_dma_ranges()
543 for_each_of_pci_range(&parser, &range) { in xgene_pcie_parse_map_dma_ranges()
544 u64 end = range.cpu_addr + range.size - 1; in xgene_pcie_parse_map_dma_ranges()
546 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", in xgene_pcie_parse_map_dma_ranges()
547 range.flags, range.cpu_addr, end, range.pci_addr); in xgene_pcie_parse_map_dma_ranges()
548 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask); in xgene_pcie_parse_map_dma_ranges()
564 struct device *dev = port->dev; in xgene_pcie_setup()
583 if (!port->link_up) in xgene_pcie_setup()
586 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); in xgene_pcie_setup()
598 struct device *dev = &pdev->dev; in xgene_pcie_probe()
599 struct device_node *dn = dev->of_node; in xgene_pcie_probe()
606 return -ENOMEM; in xgene_pcie_probe()
610 port->node = of_node_get(dn); in xgene_pcie_probe()
611 port->dev = dev; in xgene_pcie_probe()
613 port->version = XGENE_PCIE_IP_VER_UNKN; in xgene_pcie_probe()
614 if (of_device_is_compatible(port->node, "apm,xgene-pcie")) in xgene_pcie_probe()
615 port->version = XGENE_PCIE_IP_VER_1; in xgene_pcie_probe()
629 bridge->sysdata = port; in xgene_pcie_probe()
630 bridge->ops = &xgene_pcie_ops; in xgene_pcie_probe()
636 {.compatible = "apm,xgene-pcie",},
642 .name = "xgene-pcie",