Lines Matching refs:mvebu_writel

128 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)  in mvebu_writel()  function
160 mvebu_writel(port, stat, PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
170 mvebu_writel(port, stat, PCIE_STAT_OFF); in mvebu_pcie_set_local_dev_nr()
177 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(0)); in mvebu_pcie_disable_wins()
178 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); in mvebu_pcie_disable_wins()
181 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); in mvebu_pcie_disable_wins()
182 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); in mvebu_pcie_disable_wins()
183 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); in mvebu_pcie_disable_wins()
187 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); in mvebu_pcie_disable_wins()
188 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); in mvebu_pcie_disable_wins()
189 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); in mvebu_pcie_disable_wins()
192 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); in mvebu_pcie_disable_wins()
193 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); in mvebu_pcie_disable_wins()
194 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); in mvebu_pcie_disable_wins()
220 mvebu_writel(port, cs->base & 0xffff0000, in mvebu_pcie_setup_wins()
222 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); in mvebu_pcie_setup_wins()
223 mvebu_writel(port, in mvebu_pcie_setup_wins()
237 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); in mvebu_pcie_setup_wins()
238 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); in mvebu_pcie_setup_wins()
239 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, in mvebu_pcie_setup_wins()
245 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0)); in mvebu_pcie_setup_wins()
246 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); in mvebu_pcie_setup_wins()
256 mvebu_writel(port, ctrl, PCIE_CTRL_OFF); in mvebu_pcie_setup_hw()
268 mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); in mvebu_pcie_setup_hw()
273 mvebu_writel(port, cmd, PCIE_CMD_OFF); in mvebu_pcie_setup_hw()
299 mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF); in mvebu_pcie_setup_hw()
316 mvebu_writel(port, sspl, PCIE_SSPL_OFF); in mvebu_pcie_setup_hw()
319 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); in mvebu_pcie_setup_hw()
322 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); in mvebu_pcie_setup_hw()
341 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); in mvebu_pcie_setup_hw()
364 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), in mvebu_pcie_child_rd_conf()
400 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), in mvebu_pcie_child_wr_conf()
736 mvebu_writel(port, new, PCIE_CMD_OFF); in mvebu_pci_bridge_emul_base_conf_write()
784 mvebu_writel(port, ctrl, PCIE_CTRL_OFF); in mvebu_pci_bridge_emul_base_conf_write()
801 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); in mvebu_pci_bridge_emul_pcie_conf_write()
812 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); in mvebu_pci_bridge_emul_pcie_conf_write()
827 mvebu_writel(port, sspl, PCIE_SSPL_OFF); in mvebu_pci_bridge_emul_pcie_conf_write()
839 mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF); in mvebu_pci_bridge_emul_pcie_conf_write()
843 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2); in mvebu_pci_bridge_emul_pcie_conf_write()
847 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2); in mvebu_pci_bridge_emul_pcie_conf_write()
879 mvebu_writel(port, new, PCIE_CAP_PCIERR_OFF + reg); in mvebu_pci_bridge_emul_ext_conf_write()
1027 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); in mvebu_pcie_intx_irq_mask()
1041 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); in mvebu_pcie_intx_irq_unmask()
1246 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); in mvebu_pcie_resume()
1674 mvebu_writel(port, cmd, PCIE_CMD_OFF); in mvebu_pcie_remove()
1677 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); in mvebu_pcie_remove()
1680 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); in mvebu_pcie_remove()
1695 mvebu_writel(port, sspl, PCIE_SSPL_OFF); in mvebu_pcie_remove()