Lines Matching refs:advk_readl
298 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() function
308 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
396 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
411 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
422 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
491 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
497 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
503 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
532 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
538 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
550 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
565 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
576 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
592 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
597 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
615 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
632 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
661 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
689 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
755 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
768 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
769 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
787 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
798 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) in advk_pci_bridge_emul_base_conf_read()
802 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
833 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_base_conf_write()
841 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
871 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
884 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
900 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
955 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
983 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
1041 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
1043 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
1045 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
1081 bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff; in advk_sw_pci_bridge_init()
1082 bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16; in advk_sw_pci_bridge_init()
1132 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1169 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1250 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1322 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_mask()
1336 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_unmask()
1409 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1423 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1577 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; in advk_pcie_handle_pme()
1605 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1606 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1628 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1629 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1632 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1633 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1675 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1944 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_remove()
1949 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_remove()
1982 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_remove()