Lines Matching +full:x +full:- +full:rp
1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
25 #include "pcie-mobiveil.h"
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus() local
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
67 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
73 return rp->config_axi_slave_base + where; in mobiveil_pcie_map_bus()
86 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
87 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr() local
88 struct mobiveil_msi *msi = &rp->msi; in mobiveil_pcie_isr()
115 ret = generic_handle_domain_irq(rp->intx_domain, in mobiveil_pcie_isr()
135 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET); in mobiveil_pcie_isr()
139 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET); in mobiveil_pcie_isr()
147 msi_addr_lo = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
149 msi_addr_hi = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
151 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n", in mobiveil_pcie_isr()
154 generic_handle_domain_irq(msi->dev_domain, msi_data); in mobiveil_pcie_isr()
156 msi_status = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
167 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_parse_dt()
168 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_parse_dt()
169 struct device_node *node = dev->of_node; in mobiveil_pcie_parse_dt()
170 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_parse_dt() local
176 rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_parse_dt()
177 if (IS_ERR(rp->config_axi_slave_base)) in mobiveil_pcie_parse_dt()
178 return PTR_ERR(rp->config_axi_slave_base); in mobiveil_pcie_parse_dt()
179 rp->ob_io_res = res; in mobiveil_pcie_parse_dt()
184 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_parse_dt()
185 if (IS_ERR(pcie->csr_axi_slave_base)) in mobiveil_pcie_parse_dt()
186 return PTR_ERR(pcie->csr_axi_slave_base); in mobiveil_pcie_parse_dt()
187 pcie->pcie_reg_base = res->start; in mobiveil_pcie_parse_dt()
190 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) in mobiveil_pcie_parse_dt()
191 pcie->apio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
193 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) in mobiveil_pcie_parse_dt()
194 pcie->ppio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
201 phys_addr_t msg_addr = pcie->pcie_reg_base; in mobiveil_pcie_enable_msi()
202 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_pcie_enable_msi()
204 msi->num_of_vectors = PCI_NUM_MSI; in mobiveil_pcie_enable_msi()
205 msi->msi_pages_phys = (phys_addr_t)msg_addr; in mobiveil_pcie_enable_msi()
208 pcie->apb_csr_base + MSI_BASE_LO_OFFSET); in mobiveil_pcie_enable_msi()
210 pcie->apb_csr_base + MSI_BASE_HI_OFFSET); in mobiveil_pcie_enable_msi()
211 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); in mobiveil_pcie_enable_msi()
212 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); in mobiveil_pcie_enable_msi()
217 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_host_init() local
218 struct pci_host_bridge *bridge = rp->bridge; in mobiveil_host_init()
222 pcie->ib_wins_configured = 0; in mobiveil_host_init()
223 pcie->ob_wins_configured = 0; in mobiveil_host_init()
270 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0, in mobiveil_host_init()
271 CFG_WINDOW_TYPE, resource_size(rp->ob_io_res)); in mobiveil_host_init()
277 resource_list_for_each_entry(win, &bridge->windows) { in mobiveil_host_init()
278 if (resource_type(win->res) == IORESOURCE_MEM) in mobiveil_host_init()
280 else if (resource_type(win->res) == IORESOURCE_IO) in mobiveil_host_init()
286 program_ob_windows(pcie, pcie->ob_wins_configured, in mobiveil_host_init()
287 win->res->start, in mobiveil_host_init()
288 win->res->start - win->offset, in mobiveil_host_init()
289 type, resource_size(win->res)); in mobiveil_host_init()
304 struct mobiveil_root_port *rp; in mobiveil_mask_intx_irq() local
308 rp = &pcie->rp; in mobiveil_mask_intx_irq()
309 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); in mobiveil_mask_intx_irq()
310 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); in mobiveil_mask_intx_irq()
314 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); in mobiveil_mask_intx_irq()
320 struct mobiveil_root_port *rp; in mobiveil_unmask_intx_irq() local
324 rp = &pcie->rp; in mobiveil_unmask_intx_irq()
325 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); in mobiveil_unmask_intx_irq()
326 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); in mobiveil_unmask_intx_irq()
330 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); in mobiveil_unmask_intx_irq()
346 irq_set_chip_data(irq, domain->host_data); in mobiveil_pcie_intx_map()
371 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); in mobiveil_compose_msi_msg()
373 msg->address_lo = lower_32_bits(addr); in mobiveil_compose_msi_msg()
374 msg->address_hi = upper_32_bits(addr); in mobiveil_compose_msi_msg()
375 msg->data = data->hwirq; in mobiveil_compose_msi_msg()
377 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", in mobiveil_compose_msi_msg()
378 (int)data->hwirq, msg->address_hi, msg->address_lo); in mobiveil_compose_msi_msg()
384 return -EINVAL; in mobiveil_msi_set_affinity()
397 struct mobiveil_pcie *pcie = domain->host_data; in mobiveil_irq_msi_domain_alloc()
398 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_alloc()
402 mutex_lock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
404 bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors); in mobiveil_irq_msi_domain_alloc()
405 if (bit >= msi->num_of_vectors) { in mobiveil_irq_msi_domain_alloc()
406 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
407 return -ENOSPC; in mobiveil_irq_msi_domain_alloc()
410 set_bit(bit, msi->msi_irq_in_use); in mobiveil_irq_msi_domain_alloc()
412 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
415 domain->host_data, handle_level_irq, NULL, NULL); in mobiveil_irq_msi_domain_alloc()
425 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_free()
427 mutex_lock(&msi->lock); in mobiveil_irq_msi_domain_free()
429 if (!test_bit(d->hwirq, msi->msi_irq_in_use)) in mobiveil_irq_msi_domain_free()
430 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", in mobiveil_irq_msi_domain_free()
431 d->hwirq); in mobiveil_irq_msi_domain_free()
433 __clear_bit(d->hwirq, msi->msi_irq_in_use); in mobiveil_irq_msi_domain_free()
435 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_free()
444 struct device *dev = &pcie->pdev->dev; in mobiveil_allocate_msi_domains()
445 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in mobiveil_allocate_msi_domains()
446 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_allocate_msi_domains()
448 mutex_init(&msi->lock); in mobiveil_allocate_msi_domains()
449 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors, in mobiveil_allocate_msi_domains()
451 if (!msi->dev_domain) { in mobiveil_allocate_msi_domains()
453 return -ENOMEM; in mobiveil_allocate_msi_domains()
456 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in mobiveil_allocate_msi_domains()
458 msi->dev_domain); in mobiveil_allocate_msi_domains()
459 if (!msi->msi_domain) { in mobiveil_allocate_msi_domains()
461 irq_domain_remove(msi->dev_domain); in mobiveil_allocate_msi_domains()
462 return -ENOMEM; in mobiveil_allocate_msi_domains()
470 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_init_irq_domain()
471 struct device_node *node = dev->of_node; in mobiveil_pcie_init_irq_domain()
472 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_init_irq_domain() local
475 rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, in mobiveil_pcie_init_irq_domain()
478 if (!rp->intx_domain) { in mobiveil_pcie_init_irq_domain()
480 return -ENOMEM; in mobiveil_pcie_init_irq_domain()
483 raw_spin_lock_init(&rp->intx_mask_lock); in mobiveil_pcie_init_irq_domain()
491 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_integrated_interrupt_init()
492 struct device *dev = &pdev->dev; in mobiveil_pcie_integrated_interrupt_init()
493 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_integrated_interrupt_init() local
499 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_integrated_interrupt_init()
500 if (IS_ERR(pcie->apb_csr_base)) in mobiveil_pcie_integrated_interrupt_init()
501 return PTR_ERR(pcie->apb_csr_base); in mobiveil_pcie_integrated_interrupt_init()
506 rp->irq = platform_get_irq(pdev, 0); in mobiveil_pcie_integrated_interrupt_init()
507 if (rp->irq < 0) in mobiveil_pcie_integrated_interrupt_init()
508 return rp->irq; in mobiveil_pcie_integrated_interrupt_init()
517 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); in mobiveil_pcie_integrated_interrupt_init()
529 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_interrupt_init() local
531 if (rp->ops->interrupt_init) in mobiveil_pcie_interrupt_init()
532 return rp->ops->interrupt_init(pcie); in mobiveil_pcie_interrupt_init()
549 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_host_probe() local
550 struct pci_host_bridge *bridge = rp->bridge; in mobiveil_pcie_host_probe()
551 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_host_probe()
556 dev_err(dev, "Parsing DT failed, ret: %x\n", ret); in mobiveil_pcie_host_probe()
561 return -ENODEV; in mobiveil_pcie_host_probe()
580 bridge->sysdata = pcie; in mobiveil_pcie_host_probe()
581 bridge->ops = &mobiveil_pcie_ops; in mobiveil_pcie_host_probe()
585 dev_info(dev, "link bring-up failed\n"); in mobiveil_pcie_host_probe()