50 #define APPL_CTRL				0x4  macro
468 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_hot_rst_done()
470 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_hot_rst_done()
982 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
984 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
1017 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_start_link()
1019 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_start_link()
1425 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1431 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_config_controller()
1449 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1450 	appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);  in tegra_pcie_config_controller()
1613 		data = readl(pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1615 		writel(data, pcie->appl_base + APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1708 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1710 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1823 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1826 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1916 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1918 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
2327 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2331 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2397 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_resume_early()
2403 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_resume_early()