Lines Matching +full:vpcie12v +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
328 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
333 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); in tegra_pcie_icc_set()
344 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
346 * transitioning to Gen-2 speed in apply_bad_link_workaround()
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
351 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
352 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
353 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
357 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
360 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
363 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
372 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_rp_irq_handler()
373 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_rp_irq_handler()
381 if (!pcie->of_data->has_sbr_reset_fix && in tegra_pcie_rp_irq_handler()
407 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
410 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
417 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
419 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & in tegra_pcie_rp_irq_handler()
428 dev_info(pci->dev, "CDM check complete\n"); in tegra_pcie_rp_irq_handler()
432 dev_err(pci->dev, "CDM comparison mismatch\n"); in tegra_pcie_rp_irq_handler()
436 dev_err(pci->dev, "CDM Logic error\n"); in tegra_pcie_rp_irq_handler()
441 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val); in tegra_pcie_rp_irq_handler()
476 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_irq_thread()
477 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_ep_irq_thread()
480 if (test_and_clear_bit(0, &pcie->link_status)) in tegra_pcie_ep_irq_thread()
485 if (pcie->of_data->has_ltr_req_fix) in tegra_pcie_ep_irq_thread()
489 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in tegra_pcie_ep_irq_thread()
498 /* 110us for both snoop and no-snoop */ in tegra_pcie_ep_irq_thread()
518 dev_err(pcie->dev, "Failed to send LTR message\n"); in tegra_pcie_ep_irq_thread()
541 dev_dbg(pcie->dev, "Link is up with Host\n"); in tegra_pcie_ep_hard_irq()
542 set_bit(0, &pcie->link_status); in tegra_pcie_ep_hard_irq()
561 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", in tegra_pcie_ep_hard_irq()
572 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_rd_own_conf()
579 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_rd_own_conf()
582 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_rd_own_conf()
594 struct dw_pcie_rp *pp = bus->sysdata; in tegra_pcie_dw_wr_own_conf()
601 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_wr_own_conf()
604 if (!pcie->of_data->has_msix_doorbell_access_fix && in tegra_pcie_dw_wr_own_conf()
622 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l11()
624 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l11()
631 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l12()
633 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l12()
640 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
646 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
648 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + in event_counter_prog()
657 dev_get_drvdata(s->private); in aspm_state_cnt()
676 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
680 /* Re-enable counting */ in aspm_state_cnt()
683 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + in aspm_state_cnt()
691 struct dw_pcie *pci = &pcie->pci; in init_host_aspm()
695 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; in init_host_aspm()
697 pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci, in init_host_aspm()
703 dw_pcie_writel_dbi(pci, pcie->ras_des_cap + in init_host_aspm()
707 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in init_host_aspm()
709 val |= (pcie->aspm_cmrt << 8); in init_host_aspm()
710 val |= (pcie->aspm_pwr_on_t << 19); in init_host_aspm()
711 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); in init_host_aspm()
716 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); in init_host_aspm()
723 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, in init_debugfs()
744 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_enable_system_interrupts()
750 if (pcie->enable_cdm_check) { in tegra_pcie_enable_system_interrupts()
752 val |= pcie->of_data->cdm_chk_int_en_bit; in tegra_pcie_enable_system_interrupts()
761 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
763 pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w); in tegra_pcie_enable_system_interrupts()
765 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
768 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, in tegra_pcie_enable_system_interrupts()
836 struct dw_pcie *pci = &pcie->pci; in config_gen3_gen4_eq_presets()
840 for (i = 0; i < pcie->num_lanes; i++) { in config_gen3_gen4_eq_presets()
878 val |= (pcie->of_data->gen4_preset_vec << in config_gen3_gen4_eq_presets()
895 pp->bridge->ops = &tegra_pci_ops; in tegra_pcie_dw_host_init()
897 if (!pcie->pcie_cap_base) in tegra_pcie_dw_host_init()
898 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in tegra_pcie_dw_host_init()
920 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); in tegra_pcie_dw_host_init()
922 val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes); in tegra_pcie_dw_host_init()
923 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); in tegra_pcie_dw_host_init()
926 if (pcie->enable_srns) { in tegra_pcie_dw_host_init()
927 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_dw_host_init()
930 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in tegra_pcie_dw_host_init()
938 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in tegra_pcie_dw_host_init()
939 if (!pcie->supports_clkreq) { in tegra_pcie_dw_host_init()
944 if (!pcie->of_data->has_l1ss_exit_fix) { in tegra_pcie_dw_host_init()
950 if (pcie->update_fc_fixup) { in tegra_pcie_dw_host_init()
956 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in tegra_pcie_dw_host_init()
964 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_dw_start_link()
968 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_start_link()
969 enable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_start_link()
986 /* De-assert RST */ in tegra_pcie_dw_start_link()
1014 dev_info(pci->dev, "Link is down in DLL"); in tegra_pcie_dw_start_link()
1015 dev_info(pci->dev, "Trying again with DLFE disabled\n"); in tegra_pcie_dw_start_link()
1021 reset_control_assert(pcie->core_rst); in tegra_pcie_dw_start_link()
1022 reset_control_deassert(pcie->core_rst); in tegra_pcie_dw_start_link()
1046 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_dw_link_up()
1055 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_stop_link()
1070 unsigned int phy_count = pcie->phy_count; in tegra_pcie_disable_phy()
1072 while (phy_count--) { in tegra_pcie_disable_phy()
1073 phy_power_off(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1074 phy_exit(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1083 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_enable_phy()
1084 ret = phy_init(pcie->phys[i]); in tegra_pcie_enable_phy()
1088 ret = phy_power_on(pcie->phys[i]); in tegra_pcie_enable_phy()
1096 while (i--) { in tegra_pcie_enable_phy()
1097 phy_power_off(pcie->phys[i]); in tegra_pcie_enable_phy()
1099 phy_exit(pcie->phys[i]); in tegra_pcie_enable_phy()
1107 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_dw_parse_dt()
1108 struct device_node *np = pcie->dev->of_node; in tegra_pcie_dw_parse_dt()
1111 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in tegra_pcie_dw_parse_dt()
1112 if (!pcie->dbi_res) { in tegra_pcie_dw_parse_dt()
1113 dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); in tegra_pcie_dw_parse_dt()
1114 return -ENODEV; in tegra_pcie_dw_parse_dt()
1117 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); in tegra_pcie_dw_parse_dt()
1119 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); in tegra_pcie_dw_parse_dt()
1123 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", in tegra_pcie_dw_parse_dt()
1124 &pcie->aspm_pwr_on_t); in tegra_pcie_dw_parse_dt()
1126 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", in tegra_pcie_dw_parse_dt()
1129 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", in tegra_pcie_dw_parse_dt()
1130 &pcie->aspm_l0s_enter_lat); in tegra_pcie_dw_parse_dt()
1132 dev_info(pcie->dev, in tegra_pcie_dw_parse_dt()
1135 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); in tegra_pcie_dw_parse_dt()
1137 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); in tegra_pcie_dw_parse_dt()
1141 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); in tegra_pcie_dw_parse_dt()
1143 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); in tegra_pcie_dw_parse_dt()
1147 ret = of_property_count_strings(np, "phy-names"); in tegra_pcie_dw_parse_dt()
1149 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", in tegra_pcie_dw_parse_dt()
1153 pcie->phy_count = ret; in tegra_pcie_dw_parse_dt()
1155 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) in tegra_pcie_dw_parse_dt()
1156 pcie->update_fc_fixup = true; in tegra_pcie_dw_parse_dt()
1159 if (pcie->of_data->version == TEGRA194_DWC_IP_VER) { in tegra_pcie_dw_parse_dt()
1160 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) in tegra_pcie_dw_parse_dt()
1161 pcie->enable_ext_refclk = true; in tegra_pcie_dw_parse_dt()
1163 pcie->enable_ext_refclk = in tegra_pcie_dw_parse_dt()
1164 of_property_read_bool(pcie->dev->of_node, in tegra_pcie_dw_parse_dt()
1165 "nvidia,enable-ext-refclk"); in tegra_pcie_dw_parse_dt()
1168 pcie->supports_clkreq = in tegra_pcie_dw_parse_dt()
1169 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); in tegra_pcie_dw_parse_dt()
1171 pcie->enable_cdm_check = in tegra_pcie_dw_parse_dt()
1172 of_property_read_bool(np, "snps,enable-cdm-check"); in tegra_pcie_dw_parse_dt()
1174 if (pcie->of_data->version == TEGRA234_DWC_IP_VER) in tegra_pcie_dw_parse_dt()
1175 pcie->enable_srns = in tegra_pcie_dw_parse_dt()
1176 of_property_read_bool(np, "nvidia,enable-srns"); in tegra_pcie_dw_parse_dt()
1178 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) in tegra_pcie_dw_parse_dt()
1182 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); in tegra_pcie_dw_parse_dt()
1183 if (IS_ERR(pcie->pex_rst_gpiod)) { in tegra_pcie_dw_parse_dt()
1184 int err = PTR_ERR(pcie->pex_rst_gpiod); in tegra_pcie_dw_parse_dt()
1187 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1190 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1196 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, in tegra_pcie_dw_parse_dt()
1197 "nvidia,refclk-select", in tegra_pcie_dw_parse_dt()
1199 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { in tegra_pcie_dw_parse_dt()
1200 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); in tegra_pcie_dw_parse_dt()
1203 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1206 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1209 pcie->pex_refclk_sel_gpiod = NULL; in tegra_pcie_dw_parse_dt()
1223 * Controller-5 doesn't need to have its state set by BPMP-FW in in tegra_pcie_bpmp_set_ctrl_state()
1226 if (pcie->of_data->version == TEGRA194_DWC_IP_VER && pcie->cid == 5) in tegra_pcie_bpmp_set_ctrl_state()
1233 req.controller_state.pcie_controller = pcie->cid; in tegra_pcie_bpmp_set_ctrl_state()
1243 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_ctrl_state()
1258 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1261 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1271 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_pll_state()
1276 struct dw_pcie_rp *pp = &pcie->pci.pp; in tegra_pcie_downstream_dev_to_D0()
1285 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, in tegra_pcie_downstream_dev_to_D0()
1289 list_for_each_entry(child, &pp->bridge->bus->children, node) { in tegra_pcie_downstream_dev_to_D0()
1291 if (child->parent == pp->bridge->bus) { in tegra_pcie_downstream_dev_to_D0()
1298 dev_err(pcie->dev, "Failed to find downstream devices\n"); in tegra_pcie_downstream_dev_to_D0()
1302 list_for_each_entry(pdev, &root_bus->devices, bus_list) { in tegra_pcie_downstream_dev_to_D0()
1303 if (PCI_SLOT(pdev->devfn) == 0) { in tegra_pcie_downstream_dev_to_D0()
1305 dev_err(pcie->dev, in tegra_pcie_downstream_dev_to_D0()
1307 dev_name(&pdev->dev)); in tegra_pcie_downstream_dev_to_D0()
1314 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); in tegra_pcie_get_slot_regulators()
1315 if (IS_ERR(pcie->slot_ctl_3v3)) { in tegra_pcie_get_slot_regulators()
1316 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) in tegra_pcie_get_slot_regulators()
1317 return PTR_ERR(pcie->slot_ctl_3v3); in tegra_pcie_get_slot_regulators()
1319 pcie->slot_ctl_3v3 = NULL; in tegra_pcie_get_slot_regulators()
1322 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); in tegra_pcie_get_slot_regulators()
1323 if (IS_ERR(pcie->slot_ctl_12v)) { in tegra_pcie_get_slot_regulators()
1324 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) in tegra_pcie_get_slot_regulators()
1325 return PTR_ERR(pcie->slot_ctl_12v); in tegra_pcie_get_slot_regulators()
1327 pcie->slot_ctl_12v = NULL; in tegra_pcie_get_slot_regulators()
1337 if (pcie->slot_ctl_3v3) { in tegra_pcie_enable_slot_regulators()
1338 ret = regulator_enable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1340 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1341 "Failed to enable 3.3V slot supply: %d\n", ret); in tegra_pcie_enable_slot_regulators()
1346 if (pcie->slot_ctl_12v) { in tegra_pcie_enable_slot_regulators()
1347 ret = regulator_enable(pcie->slot_ctl_12v); in tegra_pcie_enable_slot_regulators()
1349 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1350 "Failed to enable 12V slot supply: %d\n", ret); in tegra_pcie_enable_slot_regulators()
1357 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) in tegra_pcie_enable_slot_regulators()
1360 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) in tegra_pcie_enable_slot_regulators()
1366 if (pcie->slot_ctl_3v3) in tegra_pcie_enable_slot_regulators()
1367 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1373 if (pcie->slot_ctl_12v) in tegra_pcie_disable_slot_regulators()
1374 regulator_disable(pcie->slot_ctl_12v); in tegra_pcie_disable_slot_regulators()
1375 if (pcie->slot_ctl_3v3) in tegra_pcie_disable_slot_regulators()
1376 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_disable_slot_regulators()
1387 dev_err(pcie->dev, in tegra_pcie_config_controller()
1388 "Failed to enable controller %u: %d\n", pcie->cid, ret); in tegra_pcie_config_controller()
1392 if (pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1395 dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret); in tegra_pcie_config_controller()
1404 ret = regulator_enable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1406 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); in tegra_pcie_config_controller()
1410 ret = clk_prepare_enable(pcie->core_clk); in tegra_pcie_config_controller()
1412 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); in tegra_pcie_config_controller()
1416 ret = reset_control_deassert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1418 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", in tegra_pcie_config_controller()
1423 if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_config_controller()
1436 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); in tegra_pcie_config_controller()
1441 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1456 if (pcie->enable_srns || pcie->enable_ext_refclk) { in tegra_pcie_config_controller()
1458 * When Tegra PCIe RP is using external clock, it cannot supply in tegra_pcie_config_controller()
1469 if (!pcie->supports_clkreq) { in tegra_pcie_config_controller()
1478 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1481 reset_control_deassert(pcie->core_rst); in tegra_pcie_config_controller()
1486 reset_control_assert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1488 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_config_controller()
1490 regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1494 if (pcie->enable_ext_refclk) in tegra_pcie_config_controller()
1506 ret = reset_control_assert(pcie->core_rst); in tegra_pcie_unconfig_controller()
1508 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1512 ret = reset_control_assert(pcie->core_apb_rst); in tegra_pcie_unconfig_controller()
1514 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1516 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_unconfig_controller()
1518 ret = regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_unconfig_controller()
1520 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); in tegra_pcie_unconfig_controller()
1524 if (pcie->enable_ext_refclk) { in tegra_pcie_unconfig_controller()
1527 dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret); in tegra_pcie_unconfig_controller()
1532 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", in tegra_pcie_unconfig_controller()
1533 pcie->cid, ret); in tegra_pcie_unconfig_controller()
1538 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_init_controller()
1539 struct dw_pcie_rp *pp = &pci->pp; in tegra_pcie_init_controller()
1546 pp->ops = &tegra_pcie_dw_host_ops; in tegra_pcie_init_controller()
1550 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); in tegra_pcie_init_controller()
1565 if (!tegra_pcie_dw_link_up(&pcie->pci)) in tegra_pcie_try_link_l2()
1572 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, in tegra_pcie_try_link_l2()
1582 if (!tegra_pcie_dw_link_up(&pcie->pci)) { in tegra_pcie_dw_pme_turnoff()
1583 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); in tegra_pcie_dw_pme_turnoff()
1598 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); in tegra_pcie_dw_pme_turnoff()
1610 * Some cards do not go to detect state even after de-asserting in tegra_pcie_dw_pme_turnoff()
1611 * PERST#. So, de-assert LTSSM to bring link to detect state. in tegra_pcie_dw_pme_turnoff()
1613 data = readl(pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1615 writel(data, pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1617 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, in tegra_pcie_dw_pme_turnoff()
1625 dev_info(pcie->dev, "Link didn't go to detect state\n"); in tegra_pcie_dw_pme_turnoff()
1628 * DBI registers may not be accessible after this as PLL-E would be in tegra_pcie_dw_pme_turnoff()
1642 dw_pcie_host_deinit(&pcie->pci.pp); in tegra_pcie_deinit_controller()
1649 struct device *dev = pcie->dev; in tegra_pcie_config_rp()
1674 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); in tegra_pcie_config_rp()
1675 if (!pcie->link_state) { in tegra_pcie_config_rp()
1676 ret = -ENOMEDIUM; in tegra_pcie_config_rp()
1680 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in tegra_pcie_config_rp()
1682 ret = -ENOMEM; in tegra_pcie_config_rp()
1686 pcie->debugfs = debugfs_create_dir(name, NULL); in tegra_pcie_config_rp()
1704 if (pcie->ep_state == EP_STATE_DISABLED) in pex_ep_event_pex_rst_assert()
1712 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, in pex_ep_event_pex_rst_assert()
1718 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); in pex_ep_event_pex_rst_assert()
1720 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_assert()
1724 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_assert()
1726 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_assert()
1728 pm_runtime_put_sync(pcie->dev); in pex_ep_event_pex_rst_assert()
1730 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_assert()
1733 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", in pex_ep_event_pex_rst_assert()
1739 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); in pex_ep_event_pex_rst_assert()
1741 pcie->ep_state = EP_STATE_DISABLED; in pex_ep_event_pex_rst_assert()
1742 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); in pex_ep_event_pex_rst_assert()
1747 struct dw_pcie *pci = &pcie->pci; in pex_ep_event_pex_rst_deassert()
1748 struct dw_pcie_ep *ep = &pci->ep; in pex_ep_event_pex_rst_deassert()
1749 struct device *dev = pcie->dev; in pex_ep_event_pex_rst_deassert()
1754 if (pcie->ep_state == EP_STATE_ENABLED) in pex_ep_event_pex_rst_deassert()
1766 dev_err(pcie->dev, "Failed to enable controller %u: %d\n", in pex_ep_event_pex_rst_deassert()
1767 pcie->cid, ret); in pex_ep_event_pex_rst_deassert()
1771 if (pcie->enable_ext_refclk) { in pex_ep_event_pex_rst_deassert()
1780 ret = clk_prepare_enable(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1786 ret = reset_control_deassert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1838 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in pex_ep_event_pex_rst_deassert()
1841 appl_writel(pcie, pcie->atu_dma_res->start & in pex_ep_event_pex_rst_deassert()
1856 reset_control_deassert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1858 if (pcie->update_fc_fixup) { in pex_ep_event_pex_rst_deassert()
1868 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in pex_ep_event_pex_rst_deassert()
1869 if (!pcie->supports_clkreq) { in pex_ep_event_pex_rst_deassert()
1874 if (!pcie->of_data->has_l1ss_exit_fix) { in pex_ep_event_pex_rst_deassert()
1880 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in pex_ep_event_pex_rst_deassert()
1884 if (pcie->enable_srns) { in pex_ep_event_pex_rst_deassert()
1885 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in pex_ep_event_pex_rst_deassert()
1888 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, in pex_ep_event_pex_rst_deassert()
1892 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in pex_ep_event_pex_rst_deassert()
1894 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1897 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1909 if (pcie->of_data->has_ltr_req_fix) { in pex_ep_event_pex_rst_deassert()
1920 pcie->ep_state = EP_STATE_ENABLED; in pex_ep_event_pex_rst_deassert()
1926 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1929 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1931 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1944 if (gpiod_get_value(pcie->pex_rst_gpiod)) in tegra_pcie_ep_pex_rst_irq()
1956 return -EINVAL; in tegra_pcie_ep_raise_legacy_irq()
1967 return -EINVAL; in tegra_pcie_ep_raise_msi_irq()
1976 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_raise_msix_irq()
1978 writel(irq, ep->msi_mem); in tegra_pcie_ep_raise_msix_irq()
2001 dev_err(pci->dev, "Unknown IRQ type\n"); in tegra_pcie_ep_raise_irq()
2002 return -EPERM; in tegra_pcie_ep_raise_irq()
2032 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_config_ep()
2033 struct device *dev = pcie->dev; in tegra_pcie_config_ep()
2038 ep = &pci->ep; in tegra_pcie_config_ep()
2039 ep->ops = &pcie_ep_ops; in tegra_pcie_config_ep()
2041 ep->page_size = SZ_64K; in tegra_pcie_config_ep()
2043 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); in tegra_pcie_config_ep()
2050 ret = gpiod_to_irq(pcie->pex_rst_gpiod); in tegra_pcie_config_ep()
2055 pcie->pex_rst_irq = (unsigned int)ret; in tegra_pcie_config_ep()
2058 pcie->cid); in tegra_pcie_config_ep()
2061 return -ENOMEM; in tegra_pcie_config_ep()
2064 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); in tegra_pcie_config_ep()
2066 pcie->ep_state = EP_STATE_DISABLED; in tegra_pcie_config_ep()
2068 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, in tegra_pcie_config_ep()
2094 struct device *dev = &pdev->dev; in tegra_pcie_dw_probe()
2108 return -ENOMEM; in tegra_pcie_dw_probe()
2110 pci = &pcie->pci; in tegra_pcie_dw_probe()
2111 pci->dev = &pdev->dev; in tegra_pcie_dw_probe()
2112 pci->ops = &tegra_dw_pcie_ops; in tegra_pcie_dw_probe()
2113 pcie->dev = &pdev->dev; in tegra_pcie_dw_probe()
2114 pcie->of_data = (struct tegra_pcie_dw_of_data *)data; in tegra_pcie_dw_probe()
2115 pci->n_fts[0] = pcie->of_data->n_fts[0]; in tegra_pcie_dw_probe()
2116 pci->n_fts[1] = pcie->of_data->n_fts[1]; in tegra_pcie_dw_probe()
2117 pp = &pci->pp; in tegra_pcie_dw_probe()
2118 pp->num_vectors = MAX_MSI_IRQS; in tegra_pcie_dw_probe()
2124 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2137 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2146 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_probe()
2147 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); in tegra_pcie_dw_probe()
2149 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); in tegra_pcie_dw_probe()
2150 if (IS_ERR(pcie->pex_ctl_supply)) { in tegra_pcie_dw_probe()
2151 ret = PTR_ERR(pcie->pex_ctl_supply); in tegra_pcie_dw_probe()
2152 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2154 PTR_ERR(pcie->pex_ctl_supply)); in tegra_pcie_dw_probe()
2158 pcie->core_clk = devm_clk_get(dev, "core"); in tegra_pcie_dw_probe()
2159 if (IS_ERR(pcie->core_clk)) { in tegra_pcie_dw_probe()
2161 PTR_ERR(pcie->core_clk)); in tegra_pcie_dw_probe()
2162 return PTR_ERR(pcie->core_clk); in tegra_pcie_dw_probe()
2165 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, in tegra_pcie_dw_probe()
2167 if (!pcie->appl_res) { in tegra_pcie_dw_probe()
2169 return -ENODEV; in tegra_pcie_dw_probe()
2172 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); in tegra_pcie_dw_probe()
2173 if (IS_ERR(pcie->appl_base)) in tegra_pcie_dw_probe()
2174 return PTR_ERR(pcie->appl_base); in tegra_pcie_dw_probe()
2176 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); in tegra_pcie_dw_probe()
2177 if (IS_ERR(pcie->core_apb_rst)) { in tegra_pcie_dw_probe()
2179 PTR_ERR(pcie->core_apb_rst)); in tegra_pcie_dw_probe()
2180 return PTR_ERR(pcie->core_apb_rst); in tegra_pcie_dw_probe()
2183 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); in tegra_pcie_dw_probe()
2185 return -ENOMEM; in tegra_pcie_dw_probe()
2187 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_dw_probe()
2188 name = kasprintf(GFP_KERNEL, "p2u-%u", i); in tegra_pcie_dw_probe()
2191 return -ENOMEM; in tegra_pcie_dw_probe()
2197 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2203 pcie->phys = phys; in tegra_pcie_dw_probe()
2209 return -ENODEV; in tegra_pcie_dw_probe()
2211 pcie->atu_dma_res = atu_dma_res; in tegra_pcie_dw_probe()
2213 pci->atu_size = resource_size(atu_dma_res); in tegra_pcie_dw_probe()
2214 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); in tegra_pcie_dw_probe()
2215 if (IS_ERR(pci->atu_base)) in tegra_pcie_dw_probe()
2216 return PTR_ERR(pci->atu_base); in tegra_pcie_dw_probe()
2218 pcie->core_rst = devm_reset_control_get(dev, "core"); in tegra_pcie_dw_probe()
2219 if (IS_ERR(pcie->core_rst)) { in tegra_pcie_dw_probe()
2221 PTR_ERR(pcie->core_rst)); in tegra_pcie_dw_probe()
2222 return PTR_ERR(pcie->core_rst); in tegra_pcie_dw_probe()
2225 pp->irq = platform_get_irq_byname(pdev, "intr"); in tegra_pcie_dw_probe()
2226 if (pp->irq < 0) in tegra_pcie_dw_probe()
2227 return pp->irq; in tegra_pcie_dw_probe()
2229 pcie->bpmp = tegra_bpmp_get(dev); in tegra_pcie_dw_probe()
2230 if (IS_ERR(pcie->bpmp)) in tegra_pcie_dw_probe()
2231 return PTR_ERR(pcie->bpmp); in tegra_pcie_dw_probe()
2235 pcie->icc_path = devm_of_icc_get(&pdev->dev, "write"); in tegra_pcie_dw_probe()
2236 ret = PTR_ERR_OR_ZERO(pcie->icc_path); in tegra_pcie_dw_probe()
2238 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2239 dev_err_probe(&pdev->dev, ret, "failed to get write interconnect\n"); in tegra_pcie_dw_probe()
2243 switch (pcie->of_data->mode) { in tegra_pcie_dw_probe()
2245 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, in tegra_pcie_dw_probe()
2246 IRQF_SHARED, "tegra-pcie-intr", pcie); in tegra_pcie_dw_probe()
2248 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2254 if (ret && ret != -ENOMEDIUM) in tegra_pcie_dw_probe()
2261 ret = devm_request_threaded_irq(dev, pp->irq, in tegra_pcie_dw_probe()
2265 "tegra-pcie-ep-intr", pcie); in tegra_pcie_dw_probe()
2267 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2281 pcie->of_data->mode); in tegra_pcie_dw_probe()
2282 ret = -EINVAL; in tegra_pcie_dw_probe()
2286 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2294 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_remove()
2295 if (!pcie->link_state) in tegra_pcie_dw_remove()
2298 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_remove()
2300 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_remove()
2302 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_remove()
2306 pm_runtime_disable(pcie->dev); in tegra_pcie_dw_remove()
2307 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_remove()
2308 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_remove()
2309 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); in tegra_pcie_dw_remove()
2317 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_suspend_late()
2319 return -EPERM; in tegra_pcie_dw_suspend_late()
2322 if (!pcie->link_state) in tegra_pcie_dw_suspend_late()
2326 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_suspend_late()
2341 if (!pcie->link_state) in tegra_pcie_dw_suspend_noirq()
2356 if (!pcie->link_state) in tegra_pcie_dw_resume_noirq()
2363 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2369 dw_pcie_setup_rc(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2371 ret = tegra_pcie_dw_start_link(&pcie->pci); in tegra_pcie_dw_resume_noirq()
2387 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_resume_early()
2389 return -ENOTSUPP; in tegra_pcie_dw_resume_early()
2392 if (!pcie->link_state) in tegra_pcie_dw_resume_early()
2396 if (!pcie->of_data->has_sbr_reset_fix) { in tegra_pcie_dw_resume_early()
2413 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { in tegra_pcie_dw_shutdown()
2414 if (!pcie->link_state) in tegra_pcie_dw_shutdown()
2417 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_shutdown()
2420 disable_irq(pcie->pci.pp.irq); in tegra_pcie_dw_shutdown()
2422 disable_irq(pcie->pci.pp.msi_irq[0]); in tegra_pcie_dw_shutdown()
2426 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_shutdown()
2428 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_shutdown()
2437 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2446 /* Gen4 - 5, 6, 8 and 9 presets enabled */
2458 /* Gen4 - 6, 8 and 9 presets enabled */
2469 /* Gen4 - 6, 8 and 9 presets enabled */
2476 .compatible = "nvidia,tegra194-pcie",
2480 .compatible = "nvidia,tegra194-pcie-ep",
2484 .compatible = "nvidia,tegra234-pcie",
2488 .compatible = "nvidia,tegra234-pcie-ep",
2506 .name = "tegra194-pcie",