Lines Matching +full:vdda_phy +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
35 #include "pcie-designware.h"
248 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
252 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
260 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
269 if (pcie->cfg->ops->ltssm_enable) in qcom_pcie_start_link()
270 pcie->cfg->ops->ltssm_enable(pcie); in qcom_pcie_start_link()
282 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
284 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
294 val = readl(pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
296 writel(val, pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
301 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_get_resources_2_1_0()
302 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_1_0()
303 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_1_0()
304 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); in qcom_pcie_get_resources_2_1_0()
307 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_1_0()
308 res->supplies[1].supply = "vdda_phy"; in qcom_pcie_get_resources_2_1_0()
309 res->supplies[2].supply = "vdda_refclk"; in qcom_pcie_get_resources_2_1_0()
310 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_1_0()
311 res->supplies); in qcom_pcie_get_resources_2_1_0()
315 res->clks[0].id = "iface"; in qcom_pcie_get_resources_2_1_0()
316 res->clks[1].id = "core"; in qcom_pcie_get_resources_2_1_0()
317 res->clks[2].id = "phy"; in qcom_pcie_get_resources_2_1_0()
318 res->clks[3].id = "aux"; in qcom_pcie_get_resources_2_1_0()
319 res->clks[4].id = "ref"; in qcom_pcie_get_resources_2_1_0()
322 ret = devm_clk_bulk_get(dev, 3, res->clks); in qcom_pcie_get_resources_2_1_0()
327 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); in qcom_pcie_get_resources_2_1_0()
331 res->resets[0].id = "pci"; in qcom_pcie_get_resources_2_1_0()
332 res->resets[1].id = "axi"; in qcom_pcie_get_resources_2_1_0()
333 res->resets[2].id = "ahb"; in qcom_pcie_get_resources_2_1_0()
334 res->resets[3].id = "por"; in qcom_pcie_get_resources_2_1_0()
335 res->resets[4].id = "phy"; in qcom_pcie_get_resources_2_1_0()
336 res->resets[5].id = "ext"; in qcom_pcie_get_resources_2_1_0()
339 res->num_resets = is_apq ? 5 : 6; in qcom_pcie_get_resources_2_1_0()
340 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_1_0()
349 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_deinit_2_1_0()
351 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_1_0()
352 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_1_0()
354 writel(1, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_deinit_2_1_0()
356 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_1_0()
361 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_init_2_1_0()
362 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_1_0()
363 struct device *dev = pci->dev; in qcom_pcie_init_2_1_0()
367 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
373 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
379 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
382 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
391 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_post_init_2_1_0()
392 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_1_0()
393 struct device *dev = pci->dev; in qcom_pcie_post_init_2_1_0()
394 struct device_node *node = dev->of_node; in qcom_pcie_post_init_2_1_0()
399 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
401 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
403 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_post_init_2_1_0()
407 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || in qcom_pcie_post_init_2_1_0()
408 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { in qcom_pcie_post_init_2_1_0()
412 pcie->parf + PARF_PCS_DEEMPH); in qcom_pcie_post_init_2_1_0()
415 pcie->parf + PARF_PCS_SWING); in qcom_pcie_post_init_2_1_0()
416 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); in qcom_pcie_post_init_2_1_0()
419 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { in qcom_pcie_post_init_2_1_0()
421 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
424 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
428 val = readl(pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
430 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) in qcom_pcie_post_init_2_1_0()
433 writel(val, pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
440 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_post_init_2_1_0()
442 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_post_init_2_1_0()
444 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_1_0()
451 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_get_resources_1_0_0()
452 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_1_0_0()
453 struct device *dev = pci->dev; in qcom_pcie_get_resources_1_0_0()
456 res->vdda = devm_regulator_get(dev, "vdda"); in qcom_pcie_get_resources_1_0_0()
457 if (IS_ERR(res->vdda)) in qcom_pcie_get_resources_1_0_0()
458 return PTR_ERR(res->vdda); in qcom_pcie_get_resources_1_0_0()
460 res->clks[0].id = "iface"; in qcom_pcie_get_resources_1_0_0()
461 res->clks[1].id = "aux"; in qcom_pcie_get_resources_1_0_0()
462 res->clks[2].id = "master_bus"; in qcom_pcie_get_resources_1_0_0()
463 res->clks[3].id = "slave_bus"; in qcom_pcie_get_resources_1_0_0()
465 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_1_0_0()
469 res->core = devm_reset_control_get_exclusive(dev, "core"); in qcom_pcie_get_resources_1_0_0()
470 return PTR_ERR_OR_ZERO(res->core); in qcom_pcie_get_resources_1_0_0()
475 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_deinit_1_0_0()
477 reset_control_assert(res->core); in qcom_pcie_deinit_1_0_0()
478 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_1_0_0()
479 regulator_disable(res->vdda); in qcom_pcie_deinit_1_0_0()
484 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_init_1_0_0()
485 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_1_0_0()
486 struct device *dev = pci->dev; in qcom_pcie_init_1_0_0()
489 ret = reset_control_deassert(res->core); in qcom_pcie_init_1_0_0()
495 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_1_0_0()
501 ret = regulator_enable(res->vdda); in qcom_pcie_init_1_0_0()
510 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_1_0_0()
512 reset_control_assert(res->core); in qcom_pcie_init_1_0_0()
520 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_1_0_0()
523 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
526 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
529 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_1_0_0()
539 val = readl(pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
541 writel(val, pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
546 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_get_resources_2_3_2()
547 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_2()
548 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_2()
551 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_3_2()
552 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_3_2()
553 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_3_2()
554 res->supplies); in qcom_pcie_get_resources_2_3_2()
558 res->clks[0].id = "aux"; in qcom_pcie_get_resources_2_3_2()
559 res->clks[1].id = "cfg"; in qcom_pcie_get_resources_2_3_2()
560 res->clks[2].id = "bus_master"; in qcom_pcie_get_resources_2_3_2()
561 res->clks[3].id = "bus_slave"; in qcom_pcie_get_resources_2_3_2()
563 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_2_3_2()
572 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_deinit_2_3_2()
574 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_3_2()
575 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_3_2()
580 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_init_2_3_2()
581 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_2()
582 struct device *dev = pci->dev; in qcom_pcie_init_2_3_2()
585 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
591 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_2_3_2()
594 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
606 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
608 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
611 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_2_3_2()
614 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
616 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
618 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
620 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
622 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
624 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
626 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_3_2()
633 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_get_resources_2_4_0()
634 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_4_0()
635 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_4_0()
636 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); in qcom_pcie_get_resources_2_4_0()
639 res->clks[0].id = "aux"; in qcom_pcie_get_resources_2_4_0()
640 res->clks[1].id = "master_bus"; in qcom_pcie_get_resources_2_4_0()
641 res->clks[2].id = "slave_bus"; in qcom_pcie_get_resources_2_4_0()
642 res->clks[3].id = "iface"; in qcom_pcie_get_resources_2_4_0()
644 /* qcom,pcie-ipq4019 is defined without "iface" */ in qcom_pcie_get_resources_2_4_0()
645 res->num_clks = is_ipq ? 3 : 4; in qcom_pcie_get_resources_2_4_0()
647 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); in qcom_pcie_get_resources_2_4_0()
651 res->resets[0].id = "axi_m"; in qcom_pcie_get_resources_2_4_0()
652 res->resets[1].id = "axi_s"; in qcom_pcie_get_resources_2_4_0()
653 res->resets[2].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_4_0()
654 res->resets[3].id = "pipe_sticky"; in qcom_pcie_get_resources_2_4_0()
655 res->resets[4].id = "pwr"; in qcom_pcie_get_resources_2_4_0()
656 res->resets[5].id = "ahb"; in qcom_pcie_get_resources_2_4_0()
657 res->resets[6].id = "pipe"; in qcom_pcie_get_resources_2_4_0()
658 res->resets[7].id = "axi_m_vmid"; in qcom_pcie_get_resources_2_4_0()
659 res->resets[8].id = "axi_s_xpu"; in qcom_pcie_get_resources_2_4_0()
660 res->resets[9].id = "parf"; in qcom_pcie_get_resources_2_4_0()
661 res->resets[10].id = "phy"; in qcom_pcie_get_resources_2_4_0()
662 res->resets[11].id = "phy_ahb"; in qcom_pcie_get_resources_2_4_0()
664 res->num_resets = is_ipq ? 12 : 6; in qcom_pcie_get_resources_2_4_0()
666 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_4_0()
675 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_deinit_2_4_0()
677 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_4_0()
678 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_4_0()
683 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_init_2_4_0()
684 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_4_0()
685 struct device *dev = pci->dev; in qcom_pcie_init_2_4_0()
688 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
696 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
704 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_4_0()
706 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
715 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_get_resources_2_3_3()
716 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_3()
717 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_3()
720 res->clks[0].id = "iface"; in qcom_pcie_get_resources_2_3_3()
721 res->clks[1].id = "axi_m"; in qcom_pcie_get_resources_2_3_3()
722 res->clks[2].id = "axi_s"; in qcom_pcie_get_resources_2_3_3()
723 res->clks[3].id = "ahb"; in qcom_pcie_get_resources_2_3_3()
724 res->clks[4].id = "aux"; in qcom_pcie_get_resources_2_3_3()
726 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_2_3_3()
730 res->rst[0].id = "axi_m"; in qcom_pcie_get_resources_2_3_3()
731 res->rst[1].id = "axi_s"; in qcom_pcie_get_resources_2_3_3()
732 res->rst[2].id = "pipe"; in qcom_pcie_get_resources_2_3_3()
733 res->rst[3].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_3_3()
734 res->rst[4].id = "sticky"; in qcom_pcie_get_resources_2_3_3()
735 res->rst[5].id = "ahb"; in qcom_pcie_get_resources_2_3_3()
736 res->rst[6].id = "sleep"; in qcom_pcie_get_resources_2_3_3()
738 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_get_resources_2_3_3()
747 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_deinit_2_3_3()
749 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_3_3()
754 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_init_2_3_3()
755 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_3()
756 struct device *dev = pci->dev; in qcom_pcie_init_2_3_3()
759 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
767 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
779 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_2_3_3()
792 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
799 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_3_3()
803 writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); in qcom_pcie_post_init_2_3_3()
805 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
807 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
809 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_2_3_3()
814 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_3()
815 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_3_3()
817 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); in qcom_pcie_post_init_2_3_3()
821 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_3_3()
823 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
825 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
827 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_3_3()
837 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_get_resources_2_7_0()
838 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_7_0()
839 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_7_0()
844 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_7_0()
845 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_7_0()
846 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_7_0()
848 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_7_0()
849 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_7_0()
850 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_7_0()
851 res->supplies); in qcom_pcie_get_resources_2_7_0()
856 res->clks[idx++].id = "aux"; in qcom_pcie_get_resources_2_7_0()
857 res->clks[idx++].id = "cfg"; in qcom_pcie_get_resources_2_7_0()
858 res->clks[idx++].id = "bus_master"; in qcom_pcie_get_resources_2_7_0()
859 res->clks[idx++].id = "bus_slave"; in qcom_pcie_get_resources_2_7_0()
860 res->clks[idx++].id = "slave_q2a"; in qcom_pcie_get_resources_2_7_0()
864 ret = devm_clk_bulk_get(dev, num_clks, res->clks); in qcom_pcie_get_resources_2_7_0()
868 res->clks[idx++].id = "tbu"; in qcom_pcie_get_resources_2_7_0()
869 res->clks[idx++].id = "ddrss_sf_tbu"; in qcom_pcie_get_resources_2_7_0()
870 res->clks[idx++].id = "aggre0"; in qcom_pcie_get_resources_2_7_0()
871 res->clks[idx++].id = "aggre1"; in qcom_pcie_get_resources_2_7_0()
872 res->clks[idx++].id = "noc_aggr"; in qcom_pcie_get_resources_2_7_0()
873 res->clks[idx++].id = "noc_aggr_4"; in qcom_pcie_get_resources_2_7_0()
874 res->clks[idx++].id = "noc_aggr_south_sf"; in qcom_pcie_get_resources_2_7_0()
875 res->clks[idx++].id = "cnoc_qx"; in qcom_pcie_get_resources_2_7_0()
876 res->clks[idx++].id = "sleep"; in qcom_pcie_get_resources_2_7_0()
877 res->clks[idx++].id = "cnoc_sf_axi"; in qcom_pcie_get_resources_2_7_0()
879 num_opt_clks = idx - num_clks; in qcom_pcie_get_resources_2_7_0()
880 res->num_clks = idx; in qcom_pcie_get_resources_2_7_0()
882 ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); in qcom_pcie_get_resources_2_7_0()
891 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_init_2_7_0()
892 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_7_0()
893 struct device *dev = pci->dev; in qcom_pcie_init_2_7_0()
897 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
903 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
907 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_7_0()
915 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_7_0()
925 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_init_2_7_0()
928 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
930 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
933 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_init_2_7_0()
936 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
938 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
940 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
942 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
945 val = readl(pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
947 writel(val, pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
949 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
951 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
955 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
957 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
964 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_7_0()
971 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_deinit_2_7_0()
973 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_7_0()
975 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_7_0()
987 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; in qcom_pcie_config_sid_1_9_0()
988 struct device *dev = pcie->pci->dev; in qcom_pcie_config_sid_1_9_0()
994 of_get_property(dev->of_node, "iommu-map", &size); in qcom_pcie_config_sid_1_9_0()
999 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1001 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1005 return -ENOMEM; in qcom_pcie_config_sid_1_9_0()
1007 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, in qcom_pcie_config_sid_1_9_0()
1017 /* Extract the SMMU SID base from the first entry of iommu-map */ in qcom_pcie_config_sid_1_9_0()
1045 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; in qcom_pcie_config_sid_1_9_0()
1056 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_get_resources_2_9_0()
1057 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_9_0()
1058 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_9_0()
1061 res->clks[0].id = "iface"; in qcom_pcie_get_resources_2_9_0()
1062 res->clks[1].id = "axi_m"; in qcom_pcie_get_resources_2_9_0()
1063 res->clks[2].id = "axi_s"; in qcom_pcie_get_resources_2_9_0()
1064 res->clks[3].id = "axi_bridge"; in qcom_pcie_get_resources_2_9_0()
1065 res->clks[4].id = "rchng"; in qcom_pcie_get_resources_2_9_0()
1067 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_2_9_0()
1071 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_9_0()
1072 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_9_0()
1073 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_9_0()
1080 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_deinit_2_9_0()
1082 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_9_0()
1087 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_init_2_9_0()
1088 struct device *dev = pcie->pci->dev; in qcom_pcie_init_2_9_0()
1091 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_9_0()
1103 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_9_0()
1111 return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_2_9_0()
1116 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_9_0()
1122 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); in qcom_pcie_post_init_2_9_0()
1124 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1126 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1128 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_2_9_0()
1130 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_post_init_2_9_0()
1132 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_9_0()
1135 pci->dbi_base + GEN3_RELATED_OFF); in qcom_pcie_post_init_2_9_0()
1140 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_9_0()
1142 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_9_0()
1146 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_9_0()
1148 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1150 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1152 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_9_0()
1158 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); in qcom_pcie_post_init_2_9_0()
1166 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
1179 ret = pcie->cfg->ops->init(pcie); in qcom_pcie_host_init()
1183 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); in qcom_pcie_host_init()
1187 ret = phy_power_on(pcie->phy); in qcom_pcie_host_init()
1191 if (pcie->cfg->ops->post_init) { in qcom_pcie_host_init()
1192 ret = pcie->cfg->ops->post_init(pcie); in qcom_pcie_host_init()
1199 if (pcie->cfg->ops->config_sid) { in qcom_pcie_host_init()
1200 ret = pcie->cfg->ops->config_sid(pcie); in qcom_pcie_host_init()
1210 phy_power_off(pcie->phy); in qcom_pcie_host_init()
1212 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_init()
1223 phy_power_off(pcie->phy); in qcom_pcie_host_deinit()
1224 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_deinit()
1344 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_init()
1347 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); in qcom_pcie_icc_init()
1348 if (IS_ERR(pcie->icc_mem)) in qcom_pcie_icc_init()
1349 return PTR_ERR(pcie->icc_mem); in qcom_pcie_icc_init()
1355 * Set an initial peak bandwidth corresponding to single-lane Gen 1 in qcom_pcie_icc_init()
1356 * for the pcie-mem path. in qcom_pcie_icc_init()
1358 ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); in qcom_pcie_icc_init()
1360 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", in qcom_pcie_icc_init()
1370 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_update()
1375 if (!pcie->icc_mem) in qcom_pcie_icc_update()
1379 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_icc_update()
1403 ret = icc_set_bw(pcie->icc_mem, 0, width * bw); in qcom_pcie_icc_update()
1405 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", in qcom_pcie_icc_update()
1412 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); in qcom_pcie_link_transition_count()
1415 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); in qcom_pcie_link_transition_count()
1418 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); in qcom_pcie_link_transition_count()
1421 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); in qcom_pcie_link_transition_count()
1424 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); in qcom_pcie_link_transition_count()
1427 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); in qcom_pcie_link_transition_count()
1434 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_debugfs()
1435 struct device *dev = pci->dev; in qcom_pcie_init_debugfs()
1438 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in qcom_pcie_init_debugfs()
1442 pcie->debugfs = debugfs_create_dir(name, NULL); in qcom_pcie_init_debugfs()
1443 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, in qcom_pcie_init_debugfs()
1450 struct device *dev = &pdev->dev; in qcom_pcie_probe()
1458 if (!pcie_cfg || !pcie_cfg->ops) { in qcom_pcie_probe()
1460 return -EINVAL; in qcom_pcie_probe()
1465 return -ENOMEM; in qcom_pcie_probe()
1469 return -ENOMEM; in qcom_pcie_probe()
1476 pci->dev = dev; in qcom_pcie_probe()
1477 pci->ops = &dw_pcie_ops; in qcom_pcie_probe()
1478 pp = &pci->pp; in qcom_pcie_probe()
1480 pcie->pci = pci; in qcom_pcie_probe()
1482 pcie->cfg = pcie_cfg; in qcom_pcie_probe()
1484 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); in qcom_pcie_probe()
1485 if (IS_ERR(pcie->reset)) { in qcom_pcie_probe()
1486 ret = PTR_ERR(pcie->reset); in qcom_pcie_probe()
1490 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); in qcom_pcie_probe()
1491 if (IS_ERR(pcie->parf)) { in qcom_pcie_probe()
1492 ret = PTR_ERR(pcie->parf); in qcom_pcie_probe()
1496 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); in qcom_pcie_probe()
1497 if (IS_ERR(pcie->elbi)) { in qcom_pcie_probe()
1498 ret = PTR_ERR(pcie->elbi); in qcom_pcie_probe()
1505 pcie->mhi = devm_ioremap_resource(dev, res); in qcom_pcie_probe()
1506 if (IS_ERR(pcie->mhi)) { in qcom_pcie_probe()
1507 ret = PTR_ERR(pcie->mhi); in qcom_pcie_probe()
1512 pcie->phy = devm_phy_optional_get(dev, "pciephy"); in qcom_pcie_probe()
1513 if (IS_ERR(pcie->phy)) { in qcom_pcie_probe()
1514 ret = PTR_ERR(pcie->phy); in qcom_pcie_probe()
1522 ret = pcie->cfg->ops->get_resources(pcie); in qcom_pcie_probe()
1526 pp->ops = &qcom_pcie_dw_ops; in qcom_pcie_probe()
1528 ret = phy_init(pcie->phy); in qcom_pcie_probe()
1542 if (pcie->mhi) in qcom_pcie_probe()
1548 phy_exit(pcie->phy); in qcom_pcie_probe()
1565 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); in qcom_pcie_suspend_noirq()
1582 * implies VDD supply will be removed and the devices may go into in qcom_pcie_suspend_noirq()
1586 if (!dw_pcie_link_up(pcie->pci)) { in qcom_pcie_suspend_noirq()
1587 qcom_pcie_host_deinit(&pcie->pci->pp); in qcom_pcie_suspend_noirq()
1588 pcie->suspended = true; in qcom_pcie_suspend_noirq()
1599 if (pcie->suspended) { in qcom_pcie_resume_noirq()
1600 ret = qcom_pcie_host_init(&pcie->pci->pp); in qcom_pcie_resume_noirq()
1604 pcie->suspended = false; in qcom_pcie_resume_noirq()
1613 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1614 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1615 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1616 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1617 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1618 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1619 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1620 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1621 { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
1622 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1623 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1624 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
1625 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
1626 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1627 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1628 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
1629 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1630 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1631 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1632 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1633 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1634 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1635 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1636 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1642 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in qcom_fixup_class()
1659 .name = "qcom-pcie",