controller/dwc/pcie-qcom.c

37 /* PARF registers */
236 	void __iomem *parf;			/* DT parf */  member
354 	writel(1, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_deinit_2_1_0()
399 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
401 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
412 		       pcie->parf + PARF_PCS_DEEMPH);  in qcom_pcie_post_init_2_1_0()
415 		       pcie->parf + PARF_PCS_SWING);  in qcom_pcie_post_init_2_1_0()
416 		writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);  in qcom_pcie_post_init_2_1_0()
421 		val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
424 		writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
428 	val = readl(pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
433 	writel(val, pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
520 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_1_0_0()
523 		u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
526 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
539 	val = readl(pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
541 	writel(val, pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
606 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
608 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
611 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_3_2()
614 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
616 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
618 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
620 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
622 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
624 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
660 	res->resets[9].id = "parf";  in qcom_pcie_get_resources_2_4_0()
803 	writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);  in qcom_pcie_post_init_2_3_3()
805 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
807 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
809 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_3_3()
814 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_3()
815 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_3_3()
925 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_init_2_7_0()
928 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
930 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
933 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_init_2_7_0()
936 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
938 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
940 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
942 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
945 	val = readl(pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
947 	writel(val, pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
949 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
951 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
987 	void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;  in qcom_pcie_config_sid_1_9_0()
999 	val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1001 	writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1122 		pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);  in qcom_pcie_post_init_2_9_0()
1124 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1126 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1128 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_9_0()
1130 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_post_init_2_9_0()
1132 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_9_0()
1140 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_9_0()
1142 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_9_0()
1158 		writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));  in qcom_pcie_post_init_2_9_0()
1490 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");  in qcom_pcie_probe()
1491 	if (IS_ERR(pcie->parf)) {  in qcom_pcie_probe()
1492 		ret = PTR_ERR(pcie->parf);  in qcom_pcie_probe()