controller/cadence/pcie-cadence.h

1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
42 /* Endpoint Bus and Device Number Register */
49 /* Endpoint Function f BAR b Configuration Registers */
71 /* Endpoint Function Configuration Register */
96 /* BAR control values applicable to both Endpoint Function and Root Complex */
117 					(((aperture) - 2) << ((bar) * 8))
124  * Endpoint Function Registers (PCI configuration space for endpoint functions)
149 	(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
184 /* Region r AXI Region Base Address Register 0 */
189 	(((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
191 /* Region r AXI Region Base Address Register 1 */
200 	(((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
216 	RP_BAR_UNDEFINED = -1,
230 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
286  * struct cdns_pcie - private data for Cadence PCIe controller drivers
287  * @reg_base: IO mapped register base
290  * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
294  * @ops: Platform-specific ops to control various inputs from Cadence PCIe
309  * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
335  * struct cdns_pcie_epf - Structure to hold info about endpoint function
337  * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers
345  * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
349  * @ob_addr: base addresses in the AXI bus where the outbound regions start
350  * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
352  * @irq_cpu_addr: base address in the CPU space where a write access triggers
363  * @epf: Structure to hold info about endpoint function
388 	writel(value, pcie->reg_base + reg);  in cdns_pcie_writel()
393 	return readl(pcie->reg_base + reg);  in cdns_pcie_readl()
410 	return (val >> (8 * offset)) & ((1 << (size * 8)) - 1);  in cdns_pcie_read_sz()
430 	mask = ~(((1 << (size * 8)) - 1) << (offset * 8));  in cdns_pcie_write_sz()
440 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;  in cdns_pcie_rp_writeb()
448 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;  in cdns_pcie_rp_writew()
455 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;  in cdns_pcie_rp_readw()
460 /* Endpoint Function register access */
464 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;  in cdns_pcie_ep_fn_writeb()
472 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;  in cdns_pcie_ep_fn_writew()
480 	writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);  in cdns_pcie_ep_fn_writel()
485 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;  in cdns_pcie_ep_fn_readw()
492 	return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);  in cdns_pcie_ep_fn_readl()
497 	if (pcie->ops->start_link)  in cdns_pcie_start_link()
498 		return pcie->ops->start_link(pcie);  in cdns_pcie_start_link()
505 	if (pcie->ops->stop_link)  in cdns_pcie_stop_link()
506 		pcie->ops->stop_link(pcie);  in cdns_pcie_stop_link()
511 	if (pcie->ops->link_up)  in cdns_pcie_link_up()
512 		return pcie->ops->link_up(pcie);  in cdns_pcie_link_up()