Lines Matching refs:hba
111 static inline struct lba_device *LBA_DEV(struct pci_hba_data *hba) in LBA_DEV() argument
113 return container_of(hba, struct lba_device, hba); in LBA_DEV()
191 u8 first_bus = d->hba.hba_bus->busn_res.start; in lba_device_present()
192 u8 last_sub_bus = d->hba.hba_bus->busn_res.end; in lba_device_present()
207 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
216 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
222 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
228 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
237 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
242 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
247 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
252 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
307 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
310 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
315 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
347 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); in lba_rd_cfg()
349 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in lba_rd_cfg()
358 LBA_CFG_RESTORE(d, d->hba.base_addr); in lba_rd_cfg()
368 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in elroy_cfg_read()
411 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in lba_wr_cfg()
420 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); in lba_wr_cfg()
421 LBA_CFG_RESTORE(d, d->hba.base_addr); in lba_wr_cfg()
456 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); in elroy_cfg_write()
458 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); in elroy_cfg_write()
460 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); in elroy_cfg_write()
464 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); in elroy_cfg_write()
485 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in mercury_cfg_read()
515 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; in mercury_cfg_write()
538 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); in mercury_cfg_write()
739 ldev->hba.io_space.name, in lba_fixup_bus()
740 ldev->hba.io_space.start, ldev->hba.io_space.end, in lba_fixup_bus()
741 ldev->hba.io_space.flags); in lba_fixup_bus()
743 ldev->hba.lmmio_space.name, in lba_fixup_bus()
744 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, in lba_fixup_bus()
745 ldev->hba.lmmio_space.flags); in lba_fixup_bus()
747 err = request_resource(&ioport_resource, &(ldev->hba.io_space)); in lba_fixup_bus()
753 if (ldev->hba.elmmio_space.flags) { in lba_fixup_bus()
755 &(ldev->hba.elmmio_space)); in lba_fixup_bus()
760 (long)ldev->hba.elmmio_space.start, in lba_fixup_bus()
761 (long)ldev->hba.elmmio_space.end); in lba_fixup_bus()
768 if (ldev->hba.lmmio_space.flags) { in lba_fixup_bus()
769 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); in lba_fixup_bus()
773 (long)ldev->hba.lmmio_space.start, in lba_fixup_bus()
774 (long)ldev->hba.lmmio_space.end); in lba_fixup_bus()
780 if (ldev->hba.gmmio_space.flags) { in lba_fixup_bus()
781 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); in lba_fixup_bus()
785 (long)ldev->hba.gmmio_space.start, in lba_fixup_bus()
786 (long)ldev->hba.gmmio_space.end); in lba_fixup_bus()
1073 lba_dev->hba.bus_num.start = p->start; in lba_pat_resources()
1074 lba_dev->hba.bus_num.end = p->end; in lba_pat_resources()
1075 lba_dev->hba.bus_num.flags = IORESOURCE_BUS; in lba_pat_resources()
1080 if (!lba_dev->hba.lmmio_space.flags) { in lba_pat_resources()
1083 lba_len = ~READ_REG32(lba_dev->hba.base_addr in lba_pat_resources()
1089 sprintf(lba_dev->hba.lmmio_name, in lba_pat_resources()
1091 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1092 lba_dev->hba.lmmio_space_offset = p->start - in lba_pat_resources()
1094 r = &lba_dev->hba.lmmio_space; in lba_pat_resources()
1095 r->name = lba_dev->hba.lmmio_name; in lba_pat_resources()
1096 } else if (!lba_dev->hba.elmmio_space.flags) { in lba_pat_resources()
1097 sprintf(lba_dev->hba.elmmio_name, in lba_pat_resources()
1099 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1100 r = &lba_dev->hba.elmmio_space; in lba_pat_resources()
1101 r->name = lba_dev->hba.elmmio_name; in lba_pat_resources()
1116 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO", in lba_pat_resources()
1117 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1118 r = &lba_dev->hba.gmmio_space; in lba_pat_resources()
1119 r->name = lba_dev->hba.gmmio_name; in lba_pat_resources()
1139 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", in lba_pat_resources()
1140 (int)lba_dev->hba.bus_num.start); in lba_pat_resources()
1141 r = &lba_dev->hba.io_space; in lba_pat_resources()
1142 r->name = lba_dev->hba.io_name; in lba_pat_resources()
1143 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); in lba_pat_resources()
1173 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; in lba_legacy_resources()
1182 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); in lba_legacy_resources()
1183 r = &(lba_dev->hba.bus_num); in lba_legacy_resources()
1192 r = &(lba_dev->hba.lmmio_space); in lba_legacy_resources()
1193 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO", in lba_legacy_resources()
1194 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1195 r->name = lba_dev->hba.lmmio_name; in lba_legacy_resources()
1264 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); in lba_legacy_resources()
1271 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); in lba_legacy_resources()
1272 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); in lba_legacy_resources()
1301 r = &(lba_dev->hba.elmmio_space); in lba_legacy_resources()
1302 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO", in lba_legacy_resources()
1303 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1304 r->name = lba_dev->hba.elmmio_name; in lba_legacy_resources()
1310 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); in lba_legacy_resources()
1317 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); in lba_legacy_resources()
1318 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); in lba_legacy_resources()
1323 r = &(lba_dev->hba.io_space); in lba_legacy_resources()
1324 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", in lba_legacy_resources()
1325 (int)lba_dev->hba.bus_num.start); in lba_legacy_resources()
1326 r->name = lba_dev->hba.io_name; in lba_legacy_resources()
1328 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; in lba_legacy_resources()
1329 …r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - … in lba_legacy_resources()
1332 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); in lba_legacy_resources()
1358 d->hba.base_addr, in lba_hw_init()
1359 READ_REG64(d->hba.base_addr + LBA_STAT_CTL), in lba_hw_init()
1360 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), in lba_hw_init()
1361 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), in lba_hw_init()
1362 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); in lba_hw_init()
1364 READ_REG64(d->hba.base_addr + LBA_ARB_MASK), in lba_hw_init()
1365 READ_REG64(d->hba.base_addr + LBA_ARB_PRI), in lba_hw_init()
1366 READ_REG64(d->hba.base_addr + LBA_ARB_MODE), in lba_hw_init()
1367 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); in lba_hw_init()
1369 READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); in lba_hw_init()
1373 printk(" %Lx", READ_REG64(d->hba.base_addr + i)); in lba_hw_init()
1387 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; in lba_hw_init()
1392 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); in lba_hw_init()
1396 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); in lba_hw_init()
1414 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1416 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1418 WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); in lba_hw_init()
1429 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { in lba_hw_init()
1440 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); in lba_hw_init()
1555 lba_dev->hba.base_addr = addr; in lba_driver_probe()
1556 lba_dev->hba.dev = dev; in lba_driver_probe()
1558 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ in lba_driver_probe()
1563 pcibios_register_hba(&lba_dev->hba); in lba_driver_probe()
1587 if (lba_dev->hba.bus_num.start < lba_next_bus) in lba_driver_probe()
1588 lba_dev->hba.bus_num.start = lba_next_bus; in lba_driver_probe()
1600 &(lba_dev->hba.lmmio_space))) { in lba_driver_probe()
1602 (long)lba_dev->hba.lmmio_space.start, in lba_driver_probe()
1603 (long)lba_dev->hba.lmmio_space.end); in lba_driver_probe()
1604 lba_dev->hba.lmmio_space.flags = 0; in lba_driver_probe()
1607 pci_add_resource_offset(&resources, &lba_dev->hba.io_space, in lba_driver_probe()
1608 HBA_PORT_BASE(lba_dev->hba.hba_num)); in lba_driver_probe()
1609 if (lba_dev->hba.elmmio_space.flags) in lba_driver_probe()
1610 pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space, in lba_driver_probe()
1611 lba_dev->hba.lmmio_space_offset); in lba_driver_probe()
1612 if (lba_dev->hba.lmmio_space.flags) in lba_driver_probe()
1613 pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space, in lba_driver_probe()
1614 lba_dev->hba.lmmio_space_offset); in lba_driver_probe()
1615 if (lba_dev->hba.gmmio_space.flags) { in lba_driver_probe()
1621 pci_add_resource(&resources, &lba_dev->hba.bus_num); in lba_driver_probe()
1624 lba_bus = lba_dev->hba.hba_bus = in lba_driver_probe()
1625 pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start, in lba_driver_probe()
1646 lba_dump_res(&lba_dev->hba.io_space, 2); in lba_driver_probe()
1648 lba_dump_res(&lba_dev->hba.lmmio_space, 2); in lba_driver_probe()