Lines Matching refs:MESON_MX_EFUSE_CNTL1
21 #define MESON_MX_EFUSE_CNTL1 0x04 macro
71 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_enable()
82 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_disable()
97 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
101 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
104 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
108 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
111 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
118 readl(efuse->base + MESON_MX_EFUSE_CNTL1); in meson_mx_efuse_read_addr()
120 err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
146 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read()
161 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read()