Lines Matching +full:restricted +full:- +full:dma +full:- +full:pool
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/blk-integrity.h>
25 #include <linux/t10-pi.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/sed-opal.h>
30 #include <linux/pci-p2pdma.h>
35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
85 return -EINVAL; in io_queue_count_set()
235 s8 nr_allocations; /* PRP list pool allocations. 0 means small
236 pool in use */
237 unsigned int dma_len; /* length of single DMA segment mapping */
246 return dev->nr_allocated_queues * 8 * dev->db_stride; in nvme_dbbuf_size()
253 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) in nvme_dbbuf_dma_alloc()
256 if (dev->dbbuf_dbs) { in nvme_dbbuf_dma_alloc()
261 memset(dev->dbbuf_dbs, 0, mem_size); in nvme_dbbuf_dma_alloc()
262 memset(dev->dbbuf_eis, 0, mem_size); in nvme_dbbuf_dma_alloc()
266 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, in nvme_dbbuf_dma_alloc()
267 &dev->dbbuf_dbs_dma_addr, in nvme_dbbuf_dma_alloc()
269 if (!dev->dbbuf_dbs) in nvme_dbbuf_dma_alloc()
271 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, in nvme_dbbuf_dma_alloc()
272 &dev->dbbuf_eis_dma_addr, in nvme_dbbuf_dma_alloc()
274 if (!dev->dbbuf_eis) in nvme_dbbuf_dma_alloc()
279 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, in nvme_dbbuf_dma_alloc()
280 dev->dbbuf_dbs_dma_addr); in nvme_dbbuf_dma_alloc()
281 dev->dbbuf_dbs = NULL; in nvme_dbbuf_dma_alloc()
283 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); in nvme_dbbuf_dma_alloc()
290 if (dev->dbbuf_dbs) { in nvme_dbbuf_dma_free()
291 dma_free_coherent(dev->dev, mem_size, in nvme_dbbuf_dma_free()
292 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); in nvme_dbbuf_dma_free()
293 dev->dbbuf_dbs = NULL; in nvme_dbbuf_dma_free()
295 if (dev->dbbuf_eis) { in nvme_dbbuf_dma_free()
296 dma_free_coherent(dev->dev, mem_size, in nvme_dbbuf_dma_free()
297 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); in nvme_dbbuf_dma_free()
298 dev->dbbuf_eis = NULL; in nvme_dbbuf_dma_free()
305 if (!dev->dbbuf_dbs || !qid) in nvme_dbbuf_init()
308 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; in nvme_dbbuf_init()
309 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; in nvme_dbbuf_init()
310 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; in nvme_dbbuf_init()
311 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; in nvme_dbbuf_init()
316 if (!nvmeq->qid) in nvme_dbbuf_free()
319 nvmeq->dbbuf_sq_db = NULL; in nvme_dbbuf_free()
320 nvmeq->dbbuf_cq_db = NULL; in nvme_dbbuf_free()
321 nvmeq->dbbuf_sq_ei = NULL; in nvme_dbbuf_free()
322 nvmeq->dbbuf_cq_ei = NULL; in nvme_dbbuf_free()
330 if (!dev->dbbuf_dbs) in nvme_dbbuf_set()
334 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); in nvme_dbbuf_set()
335 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); in nvme_dbbuf_set()
337 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { in nvme_dbbuf_set()
338 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); in nvme_dbbuf_set()
342 for (i = 1; i <= dev->online_queues; i++) in nvme_dbbuf_set()
343 nvme_dbbuf_free(&dev->queues[i]); in nvme_dbbuf_set()
349 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); in nvme_dbbuf_need_event()
393 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); in nvme_pci_npages_prp()
400 struct nvme_queue *nvmeq = &dev->queues[0]; in nvme_admin_init_hctx()
403 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); in nvme_admin_init_hctx()
405 hctx->driver_data = nvmeq; in nvme_admin_init_hctx()
413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; in nvme_init_hctx()
415 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); in nvme_init_hctx()
416 hctx->driver_data = nvmeq; in nvme_init_hctx()
426 nvme_req(req)->ctrl = set->driver_data; in nvme_pci_init_request()
427 nvme_req(req)->cmd = &iod->cmd; in nvme_pci_init_request()
434 if (dev->num_vecs > 1) in queue_irq_offset()
442 struct nvme_dev *dev = to_nvme_dev(set->driver_data); in nvme_pci_map_queues()
446 for (i = 0, qoff = 0; i < set->nr_maps; i++) { in nvme_pci_map_queues()
447 struct blk_mq_queue_map *map = &set->map[i]; in nvme_pci_map_queues()
449 map->nr_queues = dev->io_queues[i]; in nvme_pci_map_queues()
450 if (!map->nr_queues) { in nvme_pci_map_queues()
457 * affinity), so use the regular blk-mq cpu mapping in nvme_pci_map_queues()
459 map->queue_offset = qoff; in nvme_pci_map_queues()
461 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); in nvme_pci_map_queues()
464 qoff += map->nr_queues; in nvme_pci_map_queues()
465 offset += map->nr_queues; in nvme_pci_map_queues()
475 u16 next_tail = nvmeq->sq_tail + 1; in nvme_write_sq_db()
477 if (next_tail == nvmeq->q_depth) in nvme_write_sq_db()
479 if (next_tail != nvmeq->last_sq_tail) in nvme_write_sq_db()
483 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, in nvme_write_sq_db()
484 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) in nvme_write_sq_db()
485 writel(nvmeq->sq_tail, nvmeq->q_db); in nvme_write_sq_db()
486 nvmeq->last_sq_tail = nvmeq->sq_tail; in nvme_write_sq_db()
492 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), in nvme_sq_copy_cmd()
494 if (++nvmeq->sq_tail == nvmeq->q_depth) in nvme_sq_copy_cmd()
495 nvmeq->sq_tail = 0; in nvme_sq_copy_cmd()
500 struct nvme_queue *nvmeq = hctx->driver_data; in nvme_commit_rqs()
502 spin_lock(&nvmeq->sq_lock); in nvme_commit_rqs()
503 if (nvmeq->sq_tail != nvmeq->last_sq_tail) in nvme_commit_rqs()
505 spin_unlock(&nvmeq->sq_lock); in nvme_commit_rqs()
511 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; in nvme_pci_use_sgls()
516 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) in nvme_pci_use_sgls()
518 if (!nvmeq->qid) in nvme_pci_use_sgls()
527 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; in nvme_free_prps()
529 dma_addr_t dma_addr = iod->first_dma; in nvme_free_prps()
532 for (i = 0; i < iod->nr_allocations; i++) { in nvme_free_prps()
533 __le64 *prp_list = iod->list[i].prp_list; in nvme_free_prps()
536 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); in nvme_free_prps()
545 if (iod->dma_len) { in nvme_unmap_data()
546 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, in nvme_unmap_data()
551 WARN_ON_ONCE(!iod->sgt.nents); in nvme_unmap_data()
553 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); in nvme_unmap_data()
555 if (iod->nr_allocations == 0) in nvme_unmap_data()
556 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list, in nvme_unmap_data()
557 iod->first_dma); in nvme_unmap_data()
558 else if (iod->nr_allocations == 1) in nvme_unmap_data()
559 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list, in nvme_unmap_data()
560 iod->first_dma); in nvme_unmap_data()
563 mempool_free(iod->sgt.sgl, dev->iod_mempool); in nvme_unmap_data()
575 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), in nvme_print_sgl()
584 struct dma_pool *pool; in nvme_pci_setup_prps() local
586 struct scatterlist *sg = iod->sgt.sgl; in nvme_pci_setup_prps()
589 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); in nvme_pci_setup_prps()
594 length -= (NVME_CTRL_PAGE_SIZE - offset); in nvme_pci_setup_prps()
596 iod->first_dma = 0; in nvme_pci_setup_prps()
600 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); in nvme_pci_setup_prps()
602 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); in nvme_pci_setup_prps()
610 iod->first_dma = dma_addr; in nvme_pci_setup_prps()
616 pool = dev->prp_small_pool; in nvme_pci_setup_prps()
617 iod->nr_allocations = 0; in nvme_pci_setup_prps()
619 pool = dev->prp_page_pool; in nvme_pci_setup_prps()
620 iod->nr_allocations = 1; in nvme_pci_setup_prps()
623 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); in nvme_pci_setup_prps()
625 iod->nr_allocations = -1; in nvme_pci_setup_prps()
628 iod->list[0].prp_list = prp_list; in nvme_pci_setup_prps()
629 iod->first_dma = prp_dma; in nvme_pci_setup_prps()
634 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); in nvme_pci_setup_prps()
637 iod->list[iod->nr_allocations++].prp_list = prp_list; in nvme_pci_setup_prps()
638 prp_list[0] = old_prp_list[i - 1]; in nvme_pci_setup_prps()
639 old_prp_list[i - 1] = cpu_to_le64(prp_dma); in nvme_pci_setup_prps()
643 dma_len -= NVME_CTRL_PAGE_SIZE; in nvme_pci_setup_prps()
645 length -= NVME_CTRL_PAGE_SIZE; in nvme_pci_setup_prps()
657 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); in nvme_pci_setup_prps()
658 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); in nvme_pci_setup_prps()
664 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), in nvme_pci_setup_prps()
666 blk_rq_payload_bytes(req), iod->sgt.nents); in nvme_pci_setup_prps()
673 sge->addr = cpu_to_le64(sg_dma_address(sg)); in nvme_pci_sgl_set_data()
674 sge->length = cpu_to_le32(sg_dma_len(sg)); in nvme_pci_sgl_set_data()
675 sge->type = NVME_SGL_FMT_DATA_DESC << 4; in nvme_pci_sgl_set_data()
681 sge->addr = cpu_to_le64(dma_addr); in nvme_pci_sgl_set_seg()
682 sge->length = cpu_to_le32(entries * sizeof(*sge)); in nvme_pci_sgl_set_seg()
683 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; in nvme_pci_sgl_set_seg()
690 struct dma_pool *pool; in nvme_pci_setup_sgls() local
692 struct scatterlist *sg = iod->sgt.sgl; in nvme_pci_setup_sgls()
693 unsigned int entries = iod->sgt.nents; in nvme_pci_setup_sgls()
698 cmd->flags = NVME_CMD_SGL_METABUF; in nvme_pci_setup_sgls()
701 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); in nvme_pci_setup_sgls()
706 pool = dev->prp_small_pool; in nvme_pci_setup_sgls()
707 iod->nr_allocations = 0; in nvme_pci_setup_sgls()
709 pool = dev->prp_page_pool; in nvme_pci_setup_sgls()
710 iod->nr_allocations = 1; in nvme_pci_setup_sgls()
713 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); in nvme_pci_setup_sgls()
715 iod->nr_allocations = -1; in nvme_pci_setup_sgls()
719 iod->list[0].sg_list = sg_list; in nvme_pci_setup_sgls()
720 iod->first_dma = sgl_dma; in nvme_pci_setup_sgls()
722 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); in nvme_pci_setup_sgls()
726 } while (--entries > 0); in nvme_pci_setup_sgls()
736 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); in nvme_setup_prp_simple()
737 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; in nvme_setup_prp_simple()
739 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); in nvme_setup_prp_simple()
740 if (dma_mapping_error(dev->dev, iod->first_dma)) in nvme_setup_prp_simple()
742 iod->dma_len = bv->bv_len; in nvme_setup_prp_simple()
744 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); in nvme_setup_prp_simple()
745 if (bv->bv_len > first_prp_len) in nvme_setup_prp_simple()
746 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); in nvme_setup_prp_simple()
748 cmnd->dptr.prp2 = 0; in nvme_setup_prp_simple()
758 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); in nvme_setup_sgl_simple()
759 if (dma_mapping_error(dev->dev, iod->first_dma)) in nvme_setup_sgl_simple()
761 iod->dma_len = bv->bv_len; in nvme_setup_sgl_simple()
763 cmnd->flags = NVME_CMD_SGL_METABUF; in nvme_setup_sgl_simple()
764 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); in nvme_setup_sgl_simple()
765 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); in nvme_setup_sgl_simple()
766 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; in nvme_setup_sgl_simple()
778 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; in nvme_map_data()
782 if ((bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) + in nvme_map_data()
785 &cmnd->rw, &bv); in nvme_map_data()
787 if (nvmeq->qid && sgl_threshold && in nvme_map_data()
788 nvme_ctrl_sgl_supported(&dev->ctrl)) in nvme_map_data()
790 &cmnd->rw, &bv); in nvme_map_data()
794 iod->dma_len = 0; in nvme_map_data()
795 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); in nvme_map_data()
796 if (!iod->sgt.sgl) in nvme_map_data()
798 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); in nvme_map_data()
799 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); in nvme_map_data()
800 if (!iod->sgt.orig_nents) in nvme_map_data()
803 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), in nvme_map_data()
806 if (rc == -EREMOTEIO) in nvme_map_data()
811 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents)) in nvme_map_data()
812 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); in nvme_map_data()
814 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); in nvme_map_data()
820 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); in nvme_map_data()
822 mempool_free(iod->sgt.sgl, dev->iod_mempool); in nvme_map_data()
832 iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0); in nvme_map_metadata()
833 if (dma_mapping_error(dev->dev, iod->meta_dma)) in nvme_map_metadata()
835 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); in nvme_map_metadata()
844 iod->aborted = false; in nvme_prep_rq()
845 iod->nr_allocations = -1; in nvme_prep_rq()
846 iod->sgt.nents = 0; in nvme_prep_rq()
848 ret = nvme_setup_cmd(req->q->queuedata, req); in nvme_prep_rq()
853 ret = nvme_map_data(dev, req, &iod->cmd); in nvme_prep_rq()
859 ret = nvme_map_metadata(dev, req, &iod->cmd); in nvme_prep_rq()
880 struct nvme_queue *nvmeq = hctx->driver_data; in nvme_queue_rq()
881 struct nvme_dev *dev = nvmeq->dev; in nvme_queue_rq()
882 struct request *req = bd->rq; in nvme_queue_rq()
890 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) in nvme_queue_rq()
893 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) in nvme_queue_rq()
894 return nvme_fail_nonready_command(&dev->ctrl, req); in nvme_queue_rq()
899 spin_lock(&nvmeq->sq_lock); in nvme_queue_rq()
900 nvme_sq_copy_cmd(nvmeq, &iod->cmd); in nvme_queue_rq()
901 nvme_write_sq_db(nvmeq, bd->last); in nvme_queue_rq()
902 spin_unlock(&nvmeq->sq_lock); in nvme_queue_rq()
910 spin_lock(&nvmeq->sq_lock); in nvme_submit_cmds()
914 nvme_sq_copy_cmd(nvmeq, &iod->cmd); in nvme_submit_cmds()
917 spin_unlock(&nvmeq->sq_lock); in nvme_submit_cmds()
926 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) in nvme_prep_rq_batch()
928 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) in nvme_prep_rq_batch()
931 req->mq_hctx->tags->rqs[req->tag] = req; in nvme_prep_rq_batch()
932 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; in nvme_prep_rq_batch()
944 if (nvmeq && nvmeq != req->mq_hctx->driver_data) in nvme_queue_rqs()
946 nvmeq = req->mq_hctx->driver_data; in nvme_queue_rqs()
961 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; in nvme_pci_unmap_rq()
962 struct nvme_dev *dev = nvmeq->dev; in nvme_pci_unmap_rq()
967 dma_unmap_page(dev->dev, iod->meta_dma, in nvme_pci_unmap_rq()
989 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; in nvme_cqe_pending()
991 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; in nvme_cqe_pending()
996 u16 head = nvmeq->cq_head; in nvme_ring_cq_doorbell()
998 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, in nvme_ring_cq_doorbell()
999 nvmeq->dbbuf_cq_ei)) in nvme_ring_cq_doorbell()
1000 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); in nvme_ring_cq_doorbell()
1005 if (!nvmeq->qid) in nvme_queue_tagset()
1006 return nvmeq->dev->admin_tagset.tags[0]; in nvme_queue_tagset()
1007 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; in nvme_queue_tagset()
1013 struct nvme_completion *cqe = &nvmeq->cqes[idx]; in nvme_handle_cqe()
1014 __u16 command_id = READ_ONCE(cqe->command_id); in nvme_handle_cqe()
1023 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { in nvme_handle_cqe()
1024 nvme_complete_async_event(&nvmeq->dev->ctrl, in nvme_handle_cqe()
1025 cqe->status, &cqe->result); in nvme_handle_cqe()
1031 dev_warn(nvmeq->dev->ctrl.device, in nvme_handle_cqe()
1033 command_id, le16_to_cpu(cqe->sq_id)); in nvme_handle_cqe()
1037 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); in nvme_handle_cqe()
1038 if (!nvme_try_complete_req(req, cqe->status, cqe->result) && in nvme_handle_cqe()
1039 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, in nvme_handle_cqe()
1046 u32 tmp = nvmeq->cq_head + 1; in nvme_update_cq_head()
1048 if (tmp == nvmeq->q_depth) { in nvme_update_cq_head()
1049 nvmeq->cq_head = 0; in nvme_update_cq_head()
1050 nvmeq->cq_phase ^= 1; in nvme_update_cq_head()
1052 nvmeq->cq_head = tmp; in nvme_update_cq_head()
1064 * load-load control dependency between phase and the rest of in nvme_poll_cq()
1068 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); in nvme_poll_cq()
1105 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); in nvme_poll_irqdisable()
1107 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); in nvme_poll_irqdisable()
1109 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); in nvme_poll_irqdisable()
1111 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); in nvme_poll_irqdisable()
1116 struct nvme_queue *nvmeq = hctx->driver_data; in nvme_poll()
1122 spin_lock(&nvmeq->cq_poll_lock); in nvme_poll()
1124 spin_unlock(&nvmeq->cq_poll_lock); in nvme_poll()
1132 struct nvme_queue *nvmeq = &dev->queues[0]; in nvme_pci_submit_async_event()
1138 spin_lock(&nvmeq->sq_lock); in nvme_pci_submit_async_event()
1141 spin_unlock(&nvmeq->sq_lock); in nvme_pci_submit_async_event()
1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); in adapter_delete_queue()
1160 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) in adapter_alloc_cq()
1168 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); in adapter_alloc_cq()
1170 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); in adapter_alloc_cq()
1174 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); in adapter_alloc_cq()
1180 struct nvme_ctrl *ctrl = &dev->ctrl; in adapter_alloc_sq()
1185 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't in adapter_alloc_sq()
1189 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) in adapter_alloc_sq()
1197 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); in adapter_alloc_sq()
1199 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); in adapter_alloc_sq()
1203 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); in adapter_alloc_sq()
1218 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; in abort_endio()
1220 dev_warn(nvmeq->dev->ctrl.device, in abort_endio()
1221 "Abort status: 0x%x", nvme_req(req)->status); in abort_endio()
1222 atomic_inc(&nvmeq->dev->ctrl.abort_limit); in abort_endio()
1232 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); in nvme_should_reset()
1235 switch (nvme_ctrl_state(&dev->ctrl)) { in nvme_should_reset()
1258 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, in nvme_warn_reset()
1261 dev_warn(dev->ctrl.device, in nvme_warn_reset()
1265 dev_warn(dev->ctrl.device, in nvme_warn_reset()
1272 dev_warn(dev->ctrl.device, in nvme_warn_reset()
1274 dev_warn(dev->ctrl.device, in nvme_warn_reset()
1281 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; in nvme_timeout()
1282 struct nvme_dev *dev = nvmeq->dev; in nvme_timeout()
1285 u32 csts = readl(dev->bar + NVME_REG_CSTS); in nvme_timeout()
1287 if (nvme_state_terminal(&dev->ctrl)) in nvme_timeout()
1294 if (pci_channel_offline(to_pci_dev(dev->dev))) in nvme_timeout()
1308 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) in nvme_timeout()
1309 nvme_poll(req->mq_hctx, NULL); in nvme_timeout()
1314 dev_warn(dev->ctrl.device, in nvme_timeout()
1316 req->tag, nvmeq->qid); in nvme_timeout()
1326 switch (nvme_ctrl_state(&dev->ctrl)) { in nvme_timeout()
1328 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); in nvme_timeout()
1331 dev_warn_ratelimited(dev->ctrl.device, in nvme_timeout()
1333 req->tag, nvmeq->qid); in nvme_timeout()
1334 nvme_req(req)->flags |= NVME_REQ_CANCELLED; in nvme_timeout()
1348 if (!nvmeq->qid || iod->aborted) { in nvme_timeout()
1349 dev_warn(dev->ctrl.device, in nvme_timeout()
1351 req->tag, nvmeq->qid); in nvme_timeout()
1352 nvme_req(req)->flags |= NVME_REQ_CANCELLED; in nvme_timeout()
1356 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { in nvme_timeout()
1357 atomic_inc(&dev->ctrl.abort_limit); in nvme_timeout()
1360 iod->aborted = true; in nvme_timeout()
1364 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); in nvme_timeout()
1366 dev_warn(nvmeq->dev->ctrl.device, in nvme_timeout()
1368 req->tag, in nvme_timeout()
1369 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), in nvme_timeout()
1370 nvmeq->qid); in nvme_timeout()
1372 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), in nvme_timeout()
1375 atomic_inc(&dev->ctrl.abort_limit); in nvme_timeout()
1380 abort_req->end_io = abort_endio; in nvme_timeout()
1381 abort_req->end_io_data = NULL; in nvme_timeout()
1392 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) { in nvme_timeout()
1393 if (nvme_state_terminal(&dev->ctrl)) in nvme_timeout()
1399 if (nvme_try_sched_reset(&dev->ctrl)) in nvme_timeout()
1400 nvme_unquiesce_io_queues(&dev->ctrl); in nvme_timeout()
1406 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), in nvme_free_queue()
1407 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); in nvme_free_queue()
1408 if (!nvmeq->sq_cmds) in nvme_free_queue()
1411 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { in nvme_free_queue()
1412 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), in nvme_free_queue()
1413 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); in nvme_free_queue()
1415 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), in nvme_free_queue()
1416 nvmeq->sq_cmds, nvmeq->sq_dma_addr); in nvme_free_queue()
1424 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { in nvme_free_queues()
1425 dev->ctrl.queue_count--; in nvme_free_queues()
1426 nvme_free_queue(&dev->queues[i]); in nvme_free_queues()
1432 struct nvme_queue *nvmeq = &dev->queues[qid]; in nvme_suspend_queue()
1434 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) in nvme_suspend_queue()
1440 nvmeq->dev->online_queues--; in nvme_suspend_queue()
1441 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) in nvme_suspend_queue()
1442 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); in nvme_suspend_queue()
1443 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) in nvme_suspend_queue()
1444 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq); in nvme_suspend_queue()
1451 for (i = dev->ctrl.queue_count - 1; i > 0; i--) in nvme_suspend_io_queues()
1465 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { in nvme_reap_pending_cqes()
1466 spin_lock(&dev->queues[i].cq_poll_lock); in nvme_reap_pending_cqes()
1467 nvme_poll_cq(&dev->queues[i], NULL); in nvme_reap_pending_cqes()
1468 spin_unlock(&dev->queues[i].cq_poll_lock); in nvme_reap_pending_cqes()
1475 int q_depth = dev->q_depth; in nvme_cmb_qdepth()
1479 if (q_size_aligned * nr_io_queues > dev->cmb_size) { in nvme_cmb_qdepth()
1480 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); in nvme_cmb_qdepth()
1491 return -ENOMEM; in nvme_cmb_qdepth()
1500 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_alloc_sq_cmds()
1502 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { in nvme_alloc_sq_cmds()
1503 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); in nvme_alloc_sq_cmds()
1504 if (nvmeq->sq_cmds) { in nvme_alloc_sq_cmds()
1505 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, in nvme_alloc_sq_cmds()
1506 nvmeq->sq_cmds); in nvme_alloc_sq_cmds()
1507 if (nvmeq->sq_dma_addr) { in nvme_alloc_sq_cmds()
1508 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); in nvme_alloc_sq_cmds()
1512 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); in nvme_alloc_sq_cmds()
1516 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), in nvme_alloc_sq_cmds()
1517 &nvmeq->sq_dma_addr, GFP_KERNEL); in nvme_alloc_sq_cmds()
1518 if (!nvmeq->sq_cmds) in nvme_alloc_sq_cmds()
1519 return -ENOMEM; in nvme_alloc_sq_cmds()
1525 struct nvme_queue *nvmeq = &dev->queues[qid]; in nvme_alloc_queue()
1527 if (dev->ctrl.queue_count > qid) in nvme_alloc_queue()
1530 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; in nvme_alloc_queue()
1531 nvmeq->q_depth = depth; in nvme_alloc_queue()
1532 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), in nvme_alloc_queue()
1533 &nvmeq->cq_dma_addr, GFP_KERNEL); in nvme_alloc_queue()
1534 if (!nvmeq->cqes) in nvme_alloc_queue()
1540 nvmeq->dev = dev; in nvme_alloc_queue()
1541 spin_lock_init(&nvmeq->sq_lock); in nvme_alloc_queue()
1542 spin_lock_init(&nvmeq->cq_poll_lock); in nvme_alloc_queue()
1543 nvmeq->cq_head = 0; in nvme_alloc_queue()
1544 nvmeq->cq_phase = 1; in nvme_alloc_queue()
1545 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; in nvme_alloc_queue()
1546 nvmeq->qid = qid; in nvme_alloc_queue()
1547 dev->ctrl.queue_count++; in nvme_alloc_queue()
1552 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, in nvme_alloc_queue()
1553 nvmeq->cq_dma_addr); in nvme_alloc_queue()
1555 return -ENOMEM; in nvme_alloc_queue()
1560 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); in queue_request_irq()
1561 int nr = nvmeq->dev->ctrl.instance; in queue_request_irq()
1564 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, in queue_request_irq()
1565 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); in queue_request_irq()
1567 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, in queue_request_irq()
1568 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); in queue_request_irq()
1574 struct nvme_dev *dev = nvmeq->dev; in nvme_init_queue()
1576 nvmeq->sq_tail = 0; in nvme_init_queue()
1577 nvmeq->last_sq_tail = 0; in nvme_init_queue()
1578 nvmeq->cq_head = 0; in nvme_init_queue()
1579 nvmeq->cq_phase = 1; in nvme_init_queue()
1580 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; in nvme_init_queue()
1581 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); in nvme_init_queue()
1583 dev->online_queues++; in nvme_init_queue()
1595 if (!mutex_trylock(&dev->shutdown_lock)) in nvme_setup_io_queues_trylock()
1596 return -ENODEV; in nvme_setup_io_queues_trylock()
1601 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) { in nvme_setup_io_queues_trylock()
1602 mutex_unlock(&dev->shutdown_lock); in nvme_setup_io_queues_trylock()
1603 return -ENODEV; in nvme_setup_io_queues_trylock()
1611 struct nvme_dev *dev = nvmeq->dev; in nvme_create_queue()
1615 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); in nvme_create_queue()
1622 vector = dev->num_vecs == 1 ? 0 : qid; in nvme_create_queue()
1624 set_bit(NVMEQ_POLLED, &nvmeq->flags); in nvme_create_queue()
1636 nvmeq->cq_vector = vector; in nvme_create_queue()
1648 set_bit(NVMEQ_ENABLED, &nvmeq->flags); in nvme_create_queue()
1649 mutex_unlock(&dev->shutdown_lock); in nvme_create_queue()
1653 dev->online_queues--; in nvme_create_queue()
1654 mutex_unlock(&dev->shutdown_lock); in nvme_create_queue()
1683 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { in nvme_dev_remove_admin()
1689 nvme_unquiesce_admin_queue(&dev->ctrl); in nvme_dev_remove_admin()
1690 nvme_remove_admin_tag_set(&dev->ctrl); in nvme_dev_remove_admin()
1696 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); in db_bar_size()
1701 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_remap_bar()
1703 if (size <= dev->bar_mapped_size) in nvme_remap_bar()
1706 return -ENOMEM; in nvme_remap_bar()
1707 if (dev->bar) in nvme_remap_bar()
1708 iounmap(dev->bar); in nvme_remap_bar()
1709 dev->bar = ioremap(pci_resource_start(pdev, 0), size); in nvme_remap_bar()
1710 if (!dev->bar) { in nvme_remap_bar()
1711 dev->bar_mapped_size = 0; in nvme_remap_bar()
1712 return -ENOMEM; in nvme_remap_bar()
1714 dev->bar_mapped_size = size; in nvme_remap_bar()
1715 dev->dbs = dev->bar + NVME_REG_DBS; in nvme_remap_bar()
1730 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? in nvme_pci_configure_admin_queue()
1731 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; in nvme_pci_configure_admin_queue()
1733 if (dev->subsystem && in nvme_pci_configure_admin_queue()
1734 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) in nvme_pci_configure_admin_queue()
1735 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); in nvme_pci_configure_admin_queue()
1744 result = nvme_disable_ctrl(&dev->ctrl, false); in nvme_pci_configure_admin_queue()
1752 dev->ctrl.numa_node = dev_to_node(dev->dev); in nvme_pci_configure_admin_queue()
1754 nvmeq = &dev->queues[0]; in nvme_pci_configure_admin_queue()
1755 aqa = nvmeq->q_depth - 1; in nvme_pci_configure_admin_queue()
1758 writel(aqa, dev->bar + NVME_REG_AQA); in nvme_pci_configure_admin_queue()
1759 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); in nvme_pci_configure_admin_queue()
1760 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); in nvme_pci_configure_admin_queue()
1762 result = nvme_enable_ctrl(&dev->ctrl); in nvme_pci_configure_admin_queue()
1766 nvmeq->cq_vector = 0; in nvme_pci_configure_admin_queue()
1770 dev->online_queues--; in nvme_pci_configure_admin_queue()
1774 set_bit(NVMEQ_ENABLED, &nvmeq->flags); in nvme_pci_configure_admin_queue()
1783 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { in nvme_create_io_queues()
1784 if (nvme_alloc_queue(dev, i, dev->q_depth)) { in nvme_create_io_queues()
1785 ret = -ENOMEM; in nvme_create_io_queues()
1790 max = min(dev->max_qid, dev->ctrl.queue_count - 1); in nvme_create_io_queues()
1791 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { in nvme_create_io_queues()
1792 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + in nvme_create_io_queues()
1793 dev->io_queues[HCTX_TYPE_READ]; in nvme_create_io_queues()
1798 for (i = dev->online_queues; i <= max; i++) { in nvme_create_io_queues()
1801 ret = nvme_create_queue(&dev->queues[i], i, polled); in nvme_create_io_queues()
1817 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; in nvme_cmb_size_unit()
1824 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; in nvme_cmb_size()
1831 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_map_cmb()
1834 if (dev->cmb_size) in nvme_map_cmb()
1837 if (NVME_CAP_CMBS(dev->ctrl.cap)) in nvme_map_cmb()
1838 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); in nvme_map_cmb()
1840 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); in nvme_map_cmb()
1841 if (!dev->cmbsz) in nvme_map_cmb()
1843 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); in nvme_map_cmb()
1846 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); in nvme_map_cmb()
1847 bar = NVME_CMB_BIR(dev->cmbloc); in nvme_map_cmb()
1857 if (NVME_CAP_CMBS(dev->ctrl.cap)) { in nvme_map_cmb()
1860 dev->bar + NVME_REG_CMBMSC); in nvme_map_cmb()
1868 if (size > bar_size - offset) in nvme_map_cmb()
1869 size = bar_size - offset; in nvme_map_cmb()
1872 dev_warn(dev->ctrl.device, in nvme_map_cmb()
1877 dev->cmb_size = size; in nvme_map_cmb()
1878 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); in nvme_map_cmb()
1880 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == in nvme_map_cmb()
1889 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; in nvme_set_host_mem()
1890 u64 dma_addr = dev->host_mem_descs_dma; in nvme_set_host_mem()
1900 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); in nvme_set_host_mem()
1902 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); in nvme_set_host_mem()
1904 dev_warn(dev->ctrl.device, in nvme_set_host_mem()
1908 dev->hmb = bits & NVME_HOST_MEM_ENABLE; in nvme_set_host_mem()
1917 for (i = 0; i < dev->nr_host_mem_descs; i++) { in nvme_free_host_mem()
1918 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; in nvme_free_host_mem()
1919 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; in nvme_free_host_mem()
1921 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], in nvme_free_host_mem()
1922 le64_to_cpu(desc->addr), in nvme_free_host_mem()
1926 kfree(dev->host_mem_desc_bufs); in nvme_free_host_mem()
1927 dev->host_mem_desc_bufs = NULL; in nvme_free_host_mem()
1928 dma_free_coherent(dev->dev, dev->host_mem_descs_size, in nvme_free_host_mem()
1929 dev->host_mem_descs, dev->host_mem_descs_dma); in nvme_free_host_mem()
1930 dev->host_mem_descs = NULL; in nvme_free_host_mem()
1931 dev->host_mem_descs_size = 0; in nvme_free_host_mem()
1932 dev->nr_host_mem_descs = 0; in nvme_free_host_mem()
1945 tmp = (preferred + chunk_size - 1); in __nvme_alloc_host_mem()
1949 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) in __nvme_alloc_host_mem()
1950 max_entries = dev->ctrl.hmmaxd; in __nvme_alloc_host_mem()
1953 descs = dma_alloc_coherent(dev->dev, descs_size, &descs_dma, in __nvme_alloc_host_mem()
1965 len = min_t(u64, chunk_size, preferred - size); in __nvme_alloc_host_mem()
1966 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, in __nvme_alloc_host_mem()
1979 dev->nr_host_mem_descs = i; in __nvme_alloc_host_mem()
1980 dev->host_mem_size = size; in __nvme_alloc_host_mem()
1981 dev->host_mem_descs = descs; in __nvme_alloc_host_mem()
1982 dev->host_mem_descs_dma = descs_dma; in __nvme_alloc_host_mem()
1983 dev->host_mem_descs_size = descs_size; in __nvme_alloc_host_mem()
1984 dev->host_mem_desc_bufs = bufs; in __nvme_alloc_host_mem()
1988 while (--i >= 0) { in __nvme_alloc_host_mem()
1991 dma_free_attrs(dev->dev, size, bufs[i], in __nvme_alloc_host_mem()
1998 dma_free_coherent(dev->dev, descs_size, descs, descs_dma); in __nvme_alloc_host_mem()
2000 dev->host_mem_descs = NULL; in __nvme_alloc_host_mem()
2001 return -ENOMEM; in __nvme_alloc_host_mem()
2007 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); in nvme_alloc_host_mem()
2013 if (!min || dev->host_mem_size >= min) in nvme_alloc_host_mem()
2019 return -ENOMEM; in nvme_alloc_host_mem()
2025 u64 preferred = (u64)dev->ctrl.hmpre * 4096; in nvme_setup_host_mem()
2026 u64 min = (u64)dev->ctrl.hmmin * 4096; in nvme_setup_host_mem()
2030 if (!dev->ctrl.hmpre) in nvme_setup_host_mem()
2035 dev_warn(dev->ctrl.device, in nvme_setup_host_mem()
2045 if (dev->host_mem_descs) { in nvme_setup_host_mem()
2046 if (dev->host_mem_size >= min) in nvme_setup_host_mem()
2052 if (!dev->host_mem_descs) { in nvme_setup_host_mem()
2054 dev_warn(dev->ctrl.device, in nvme_setup_host_mem()
2059 dev_info(dev->ctrl.device, in nvme_setup_host_mem()
2061 dev->host_mem_size >> ilog2(SZ_1M)); in nvme_setup_host_mem()
2076 ndev->cmbloc, ndev->cmbsz); in cmb_show()
2085 return sysfs_emit(buf, "%u\n", ndev->cmbloc); in cmbloc_show()
2094 return sysfs_emit(buf, "%u\n", ndev->cmbsz); in cmbsz_show()
2103 return sysfs_emit(buf, "%d\n", ndev->hmb); in hmb_show()
2114 return -EINVAL; in hmb_store()
2116 if (new == ndev->hmb) in hmb_store()
2144 if (!dev->cmbsz) in nvme_pci_attrs_are_visible()
2147 if (a == &dev_attr_hmb.attr && !ctrl->hmpre) in nvme_pci_attrs_are_visible()
2150 return a->mode; in nvme_pci_attrs_are_visible()
2174 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group); in nvme_update_attrs()
2183 struct nvme_dev *dev = affd->priv; in nvme_calc_irq_sets()
2184 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; in nvme_calc_irq_sets()
2205 nr_read_queues = nrirqs - nr_write_queues; in nvme_calc_irq_sets()
2208 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; in nvme_calc_irq_sets()
2209 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; in nvme_calc_irq_sets()
2210 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; in nvme_calc_irq_sets()
2211 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; in nvme_calc_irq_sets()
2212 affd->nr_sets = nr_read_queues ? 2 : 1; in nvme_calc_irq_sets()
2217 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_setup_irqs()
2228 * left over for non-polled I/O. in nvme_setup_irqs()
2230 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); in nvme_setup_irqs()
2231 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; in nvme_setup_irqs()
2237 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; in nvme_setup_irqs()
2238 dev->io_queues[HCTX_TYPE_READ] = 0; in nvme_setup_irqs()
2241 * We need interrupts for the admin queue and each non-polled I/O queue, in nvme_setup_irqs()
2246 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) in nvme_setup_irqs()
2247 irq_queues += (nr_io_queues - poll_queues); in nvme_setup_irqs()
2248 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI) in nvme_setup_irqs()
2260 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) in nvme_max_io_queues()
2262 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; in nvme_max_io_queues()
2267 struct nvme_queue *adminq = &dev->queues[0]; in nvme_setup_io_queues()
2268 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_setup_io_queues()
2277 dev->nr_write_queues = write_queues; in nvme_setup_io_queues()
2278 dev->nr_poll_queues = poll_queues; in nvme_setup_io_queues()
2280 nr_io_queues = dev->nr_allocated_queues - 1; in nvme_setup_io_queues()
2281 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); in nvme_setup_io_queues()
2298 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) in nvme_setup_io_queues()
2301 if (dev->cmb_use_sqes) { in nvme_setup_io_queues()
2305 dev->q_depth = result; in nvme_setup_io_queues()
2306 dev->ctrl.sqsize = result - 1; in nvme_setup_io_queues()
2308 dev->cmb_use_sqes = false; in nvme_setup_io_queues()
2317 if (!--nr_io_queues) { in nvme_setup_io_queues()
2318 result = -ENOMEM; in nvme_setup_io_queues()
2322 adminq->q_db = dev->dbs; in nvme_setup_io_queues()
2326 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) in nvme_setup_io_queues()
2337 result = -EIO; in nvme_setup_io_queues()
2341 dev->num_vecs = result; in nvme_setup_io_queues()
2342 result = max(result - 1, 1); in nvme_setup_io_queues()
2343 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; in nvme_setup_io_queues()
2354 set_bit(NVMEQ_ENABLED, &adminq->flags); in nvme_setup_io_queues()
2355 mutex_unlock(&dev->shutdown_lock); in nvme_setup_io_queues()
2358 if (result || dev->online_queues < 2) in nvme_setup_io_queues()
2361 if (dev->online_queues - 1 < dev->max_qid) { in nvme_setup_io_queues()
2362 nr_io_queues = dev->online_queues - 1; in nvme_setup_io_queues()
2370 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", in nvme_setup_io_queues()
2371 dev->io_queues[HCTX_TYPE_DEFAULT], in nvme_setup_io_queues()
2372 dev->io_queues[HCTX_TYPE_READ], in nvme_setup_io_queues()
2373 dev->io_queues[HCTX_TYPE_POLL]); in nvme_setup_io_queues()
2376 mutex_unlock(&dev->shutdown_lock); in nvme_setup_io_queues()
2383 struct nvme_queue *nvmeq = req->end_io_data; in nvme_del_queue_end()
2386 complete(&nvmeq->delete_done); in nvme_del_queue_end()
2393 struct nvme_queue *nvmeq = req->end_io_data; in nvme_del_cq_end()
2396 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); in nvme_del_cq_end()
2403 struct request_queue *q = nvmeq->dev->ctrl.admin_q; in nvme_delete_queue()
2408 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); in nvme_delete_queue()
2416 req->end_io = nvme_del_cq_end; in nvme_delete_queue()
2418 req->end_io = nvme_del_queue_end; in nvme_delete_queue()
2419 req->end_io_data = nvmeq; in nvme_delete_queue()
2421 init_completion(&nvmeq->delete_done); in nvme_delete_queue()
2428 int nr_queues = dev->online_queues - 1, sent = 0; in __nvme_delete_io_queues()
2434 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) in __nvme_delete_io_queues()
2436 nr_queues--; in __nvme_delete_io_queues()
2440 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; in __nvme_delete_io_queues()
2442 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, in __nvme_delete_io_queues()
2447 sent--; in __nvme_delete_io_queues()
2462 if (dev->io_queues[HCTX_TYPE_POLL]) in nvme_pci_nr_maps()
2464 if (dev->io_queues[HCTX_TYPE_READ]) in nvme_pci_nr_maps()
2471 if (!dev->ctrl.tagset) { in nvme_pci_update_nr_queues()
2472 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, in nvme_pci_update_nr_queues()
2478 if (!mutex_trylock(&dev->shutdown_lock)) in nvme_pci_update_nr_queues()
2482 if (!dev->online_queues) { in nvme_pci_update_nr_queues()
2483 mutex_unlock(&dev->shutdown_lock); in nvme_pci_update_nr_queues()
2487 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); in nvme_pci_update_nr_queues()
2489 nvme_free_queues(dev, dev->online_queues); in nvme_pci_update_nr_queues()
2490 mutex_unlock(&dev->shutdown_lock); in nvme_pci_update_nr_queues()
2496 int result = -ENOMEM; in nvme_pci_enable()
2497 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_pci_enable()
2505 if (readl(dev->bar + NVME_REG_CSTS) == -1) { in nvme_pci_enable()
2506 result = -ENODEV; in nvme_pci_enable()
2512 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll in nvme_pci_enable()
2515 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI) in nvme_pci_enable()
2521 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); in nvme_pci_enable()
2523 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, in nvme_pci_enable()
2525 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); in nvme_pci_enable()
2526 dev->dbs = dev->bar + 4096; in nvme_pci_enable()
2529 * Some Apple controllers require a non-standard SQE size. in nvme_pci_enable()
2533 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) in nvme_pci_enable()
2534 dev->io_sqes = 7; in nvme_pci_enable()
2536 dev->io_sqes = NVME_NVM_IOSQES; in nvme_pci_enable()
2538 if (dev->ctrl.quirks & NVME_QUIRK_QDEPTH_ONE) { in nvme_pci_enable()
2539 dev->q_depth = 2; in nvme_pci_enable()
2540 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && in nvme_pci_enable()
2541 (pdev->device == 0xa821 || pdev->device == 0xa822) && in nvme_pci_enable()
2542 NVME_CAP_MQES(dev->ctrl.cap) == 0) { in nvme_pci_enable()
2543 dev->q_depth = 64; in nvme_pci_enable()
2544 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " in nvme_pci_enable()
2545 "set queue depth=%u\n", dev->q_depth); in nvme_pci_enable()
2552 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && in nvme_pci_enable()
2553 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { in nvme_pci_enable()
2554 dev->q_depth = NVME_AQ_DEPTH + 2; in nvme_pci_enable()
2555 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", in nvme_pci_enable()
2556 dev->q_depth); in nvme_pci_enable()
2558 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ in nvme_pci_enable()
2578 if (dev->bar) in nvme_dev_unmap()
2579 iounmap(dev->bar); in nvme_dev_unmap()
2580 pci_release_mem_regions(to_pci_dev(dev->dev)); in nvme_dev_unmap()
2585 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_pci_ctrl_is_dead()
2590 if (pdev->error_state != pci_channel_io_normal) in nvme_pci_ctrl_is_dead()
2593 csts = readl(dev->bar + NVME_REG_CSTS); in nvme_pci_ctrl_is_dead()
2599 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl); in nvme_dev_disable()
2600 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_dev_disable()
2603 mutex_lock(&dev->shutdown_lock); in nvme_dev_disable()
2607 nvme_start_freeze(&dev->ctrl); in nvme_dev_disable()
2613 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); in nvme_dev_disable()
2616 nvme_quiesce_io_queues(&dev->ctrl); in nvme_dev_disable()
2618 if (!dead && dev->ctrl.queue_count > 0) { in nvme_dev_disable()
2620 nvme_disable_ctrl(&dev->ctrl, shutdown); in nvme_dev_disable()
2621 nvme_poll_irqdisable(&dev->queues[0]); in nvme_dev_disable()
2630 nvme_cancel_tagset(&dev->ctrl); in nvme_dev_disable()
2631 nvme_cancel_admin_tagset(&dev->ctrl); in nvme_dev_disable()
2636 * deadlocking blk-mq hot-cpu notifier. in nvme_dev_disable()
2639 nvme_unquiesce_io_queues(&dev->ctrl); in nvme_dev_disable()
2640 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) in nvme_dev_disable()
2641 nvme_unquiesce_admin_queue(&dev->ctrl); in nvme_dev_disable()
2643 mutex_unlock(&dev->shutdown_lock); in nvme_dev_disable()
2648 if (!nvme_wait_reset(&dev->ctrl)) in nvme_disable_prepare_reset()
2649 return -EBUSY; in nvme_disable_prepare_reset()
2658 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, in nvme_setup_prp_pools()
2661 if (!dev->prp_page_pool) in nvme_setup_prp_pools()
2662 return -ENOMEM; in nvme_setup_prp_pools()
2664 if (dev->ctrl.quirks & NVME_QUIRK_DMAPOOL_ALIGN_512) in nvme_setup_prp_pools()
2668 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, in nvme_setup_prp_pools()
2670 if (!dev->prp_small_pool) { in nvme_setup_prp_pools()
2671 dma_pool_destroy(dev->prp_page_pool); in nvme_setup_prp_pools()
2672 return -ENOMEM; in nvme_setup_prp_pools()
2679 dma_pool_destroy(dev->prp_page_pool); in nvme_release_prp_pools()
2680 dma_pool_destroy(dev->prp_small_pool); in nvme_release_prp_pools()
2687 dev->iod_mempool = mempool_create_node(1, in nvme_pci_alloc_iod_mempool()
2690 dev_to_node(dev->dev)); in nvme_pci_alloc_iod_mempool()
2691 if (!dev->iod_mempool) in nvme_pci_alloc_iod_mempool()
2692 return -ENOMEM; in nvme_pci_alloc_iod_mempool()
2698 if (dev->tagset.tags) in nvme_free_tagset()
2699 nvme_remove_io_tag_set(&dev->ctrl); in nvme_free_tagset()
2700 dev->ctrl.tagset = NULL; in nvme_free_tagset()
2709 put_device(dev->dev); in nvme_pci_free_ctrl()
2710 kfree(dev->queues); in nvme_pci_free_ctrl()
2718 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); in nvme_reset_work()
2721 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) { in nvme_reset_work()
2722 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", in nvme_reset_work()
2723 dev->ctrl.state); in nvme_reset_work()
2724 result = -ENODEV; in nvme_reset_work()
2732 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) in nvme_reset_work()
2734 nvme_sync_queues(&dev->ctrl); in nvme_reset_work()
2736 mutex_lock(&dev->shutdown_lock); in nvme_reset_work()
2740 nvme_unquiesce_admin_queue(&dev->ctrl); in nvme_reset_work()
2741 mutex_unlock(&dev->shutdown_lock); in nvme_reset_work()
2744 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the in nvme_reset_work()
2747 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { in nvme_reset_work()
2748 dev_warn(dev->ctrl.device, in nvme_reset_work()
2750 result = -EBUSY; in nvme_reset_work()
2754 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); in nvme_reset_work()
2773 if (dev->online_queues > 1) { in nvme_reset_work()
2775 nvme_unquiesce_io_queues(&dev->ctrl); in nvme_reset_work()
2776 nvme_wait_freeze(&dev->ctrl); in nvme_reset_work()
2779 nvme_unfreeze(&dev->ctrl); in nvme_reset_work()
2781 dev_warn(dev->ctrl.device, "IO queues lost\n"); in nvme_reset_work()
2782 nvme_mark_namespaces_dead(&dev->ctrl); in nvme_reset_work()
2783 nvme_unquiesce_io_queues(&dev->ctrl); in nvme_reset_work()
2784 nvme_remove_namespaces(&dev->ctrl); in nvme_reset_work()
2792 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { in nvme_reset_work()
2793 dev_warn(dev->ctrl.device, in nvme_reset_work()
2795 result = -ENODEV; in nvme_reset_work()
2799 nvme_start_ctrl(&dev->ctrl); in nvme_reset_work()
2803 mutex_unlock(&dev->shutdown_lock); in nvme_reset_work()
2809 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", in nvme_reset_work()
2811 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); in nvme_reset_work()
2813 nvme_sync_queues(&dev->ctrl); in nvme_reset_work()
2814 nvme_mark_namespaces_dead(&dev->ctrl); in nvme_reset_work()
2815 nvme_unquiesce_io_queues(&dev->ctrl); in nvme_reset_work()
2816 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); in nvme_reset_work()
2821 *val = readl(to_nvme_dev(ctrl)->bar + off); in nvme_pci_reg_read32()
2827 writel(val, to_nvme_dev(ctrl)->bar + off); in nvme_pci_reg_write32()
2833 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); in nvme_pci_reg_read64()
2839 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); in nvme_pci_get_address()
2841 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); in nvme_pci_get_address()
2846 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); in nvme_pci_print_device_info()
2847 struct nvme_subsystem *subsys = ctrl->subsys; in nvme_pci_print_device_info()
2849 dev_err(ctrl->device, in nvme_pci_print_device_info()
2851 pdev->vendor, pdev->device, in nvme_pci_print_device_info()
2852 nvme_strlen(subsys->model, sizeof(subsys->model)), in nvme_pci_print_device_info()
2853 subsys->model, nvme_strlen(subsys->firmware_rev, in nvme_pci_print_device_info()
2854 sizeof(subsys->firmware_rev)), in nvme_pci_print_device_info()
2855 subsys->firmware_rev); in nvme_pci_print_device_info()
2862 return dma_pci_p2pdma_supported(dev->dev); in nvme_pci_supports_pci_p2pdma()
2882 struct pci_dev *pdev = to_pci_dev(dev->dev); in nvme_dev_map()
2885 return -ENODEV; in nvme_dev_map()
2893 return -ENODEV; in nvme_dev_map()
2898 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { in check_vendor_combination_bug()
2904 * 950 PRO 256GB", but it seems to be restricted to two Dell in check_vendor_combination_bug()
2911 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { in check_vendor_combination_bug()
2914 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as in check_vendor_combination_bug()
2915 * within few minutes after bootup on a Coffee Lake board - in check_vendor_combination_bug()
2916 * ASUS PRIME Z370-A in check_vendor_combination_bug()
2919 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || in check_vendor_combination_bug()
2920 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) in check_vendor_combination_bug()
2922 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || in check_vendor_combination_bug()
2923 pdev->device == 0xa808 || pdev->device == 0xa809)) || in check_vendor_combination_bug()
2924 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { in check_vendor_combination_bug()
2934 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 || in check_vendor_combination_bug()
2935 pdev->device == 0x500f)) { in check_vendor_combination_bug()
2946 } else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) { in check_vendor_combination_bug()
2952 if (dmi_match(DMI_BOARD_NAME, "DN50Z-140HC-YD") || in check_vendor_combination_bug()
2965 if (dmi_match(DMI_BOARD_NAME, "LXKT-ZXEG-N6")) in check_vendor_combination_bug()
2974 unsigned long quirks = id->driver_data; in nvme_pci_alloc_dev()
2975 int node = dev_to_node(&pdev->dev); in nvme_pci_alloc_dev()
2977 int ret = -ENOMEM; in nvme_pci_alloc_dev()
2981 return ERR_PTR(-ENOMEM); in nvme_pci_alloc_dev()
2982 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); in nvme_pci_alloc_dev()
2983 mutex_init(&dev->shutdown_lock); in nvme_pci_alloc_dev()
2985 dev->nr_write_queues = write_queues; in nvme_pci_alloc_dev()
2986 dev->nr_poll_queues = poll_queues; in nvme_pci_alloc_dev()
2987 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; in nvme_pci_alloc_dev()
2988 dev->queues = kcalloc_node(dev->nr_allocated_queues, in nvme_pci_alloc_dev()
2990 if (!dev->queues) in nvme_pci_alloc_dev()
2993 dev->dev = get_device(&pdev->dev); in nvme_pci_alloc_dev()
2998 acpi_storage_d3(&pdev->dev)) { in nvme_pci_alloc_dev()
3003 dev_info(&pdev->dev, in nvme_pci_alloc_dev()
3007 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, in nvme_pci_alloc_dev()
3012 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) in nvme_pci_alloc_dev()
3013 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)); in nvme_pci_alloc_dev()
3015 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in nvme_pci_alloc_dev()
3016 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); in nvme_pci_alloc_dev()
3017 dma_set_max_seg_size(&pdev->dev, 0xffffffff); in nvme_pci_alloc_dev()
3020 * Limit the max command size to prevent iod->sg allocations going in nvme_pci_alloc_dev()
3023 dev->ctrl.max_hw_sectors = min_t(u32, in nvme_pci_alloc_dev()
3024 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9); in nvme_pci_alloc_dev()
3025 dev->ctrl.max_segments = NVME_MAX_SEGS; in nvme_pci_alloc_dev()
3031 dev->ctrl.max_integrity_segments = 1; in nvme_pci_alloc_dev()
3035 put_device(dev->dev); in nvme_pci_alloc_dev()
3036 kfree(dev->queues); in nvme_pci_alloc_dev()
3045 int result = -ENOMEM; in nvme_probe()
3063 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); in nvme_probe()
3069 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset, in nvme_probe()
3078 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { in nvme_probe()
3079 dev_warn(dev->ctrl.device, in nvme_probe()
3081 result = -EBUSY; in nvme_probe()
3085 result = nvme_init_ctrl_finish(&dev->ctrl, false); in nvme_probe()
3099 if (dev->online_queues > 1) { in nvme_probe()
3100 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, in nvme_probe()
3105 if (!dev->ctrl.tagset) in nvme_probe()
3106 dev_warn(dev->ctrl.device, "IO queues not created\n"); in nvme_probe()
3108 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { in nvme_probe()
3109 dev_warn(dev->ctrl.device, in nvme_probe()
3111 result = -ENODEV; in nvme_probe()
3117 nvme_start_ctrl(&dev->ctrl); in nvme_probe()
3118 nvme_put_ctrl(&dev->ctrl); in nvme_probe()
3119 flush_work(&dev->ctrl.scan_work); in nvme_probe()
3123 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); in nvme_probe()
3130 mempool_destroy(dev->iod_mempool); in nvme_probe()
3136 nvme_uninit_ctrl(&dev->ctrl); in nvme_probe()
3137 nvme_put_ctrl(&dev->ctrl); in nvme_probe()
3148 * with ->remove(). in nvme_reset_prepare()
3151 nvme_sync_queues(&dev->ctrl); in nvme_reset_prepare()
3158 if (!nvme_try_sched_reset(&dev->ctrl)) in nvme_reset_done()
3159 flush_work(&dev->ctrl.reset_work); in nvme_reset_done()
3178 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); in nvme_remove()
3182 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); in nvme_remove()
3186 flush_work(&dev->ctrl.reset_work); in nvme_remove()
3187 nvme_stop_ctrl(&dev->ctrl); in nvme_remove()
3188 nvme_remove_namespaces(&dev->ctrl); in nvme_remove()
3194 mempool_destroy(dev->iod_mempool); in nvme_remove()
3197 nvme_uninit_ctrl(&dev->ctrl); in nvme_remove()
3214 struct nvme_ctrl *ctrl = &ndev->ctrl; in nvme_resume()
3216 if (ndev->last_ps == U32_MAX || in nvme_resume()
3217 nvme_set_power_state(ctrl, ndev->last_ps) != 0) in nvme_resume()
3219 if (ctrl->hmpre && nvme_setup_host_mem(ndev)) in nvme_resume()
3231 struct nvme_ctrl *ctrl = &ndev->ctrl; in nvme_suspend()
3232 int ret = -EBUSY; in nvme_suspend()
3234 ndev->last_ps = U32_MAX; in nvme_suspend()
3241 * device does not support any non-default power states, shut down the in nvme_suspend()
3246 * down, so as to allow the platform to achieve its minimum low-power in nvme_suspend()
3249 if (pm_suspend_via_firmware() || !ctrl->npss || in nvme_suspend()
3251 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) in nvme_suspend()
3264 * non-operational power state. in nvme_suspend()
3266 if (ndev->hmb) { in nvme_suspend()
3272 ret = nvme_get_power_state(ctrl, &ndev->last_ps); in nvme_suspend()
3283 ret = nvme_set_power_state(ctrl, ctrl->npss); in nvme_suspend()
3296 ctrl->npss = 0; in nvme_suspend()
3315 return nvme_try_sched_reset(&ndev->ctrl); in nvme_simple_resume()
3342 dev_warn(dev->ctrl.device, in nvme_error_detected()
3344 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) { in nvme_error_detected()
3351 dev_warn(dev->ctrl.device, in nvme_error_detected()
3362 dev_info(dev->ctrl.device, "restart after slot reset\n"); in nvme_slot_reset()
3364 if (!nvme_try_sched_reset(&dev->ctrl)) in nvme_slot_reset()
3365 nvme_unquiesce_io_queues(&dev->ctrl); in nvme_slot_reset()
3373 flush_work(&dev->ctrl.reset_work); in nvme_error_resume()
3529 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3531 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */