615 	u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2));  in ndev_ntb_debugfs_read()
628 		u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4));  in ndev_ntb_debugfs_read()
633 	u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2));  in ndev_ntb_debugfs_read()
645 		u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4));  in ndev_ntb_debugfs_read()
655 			u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);  in ndev_ntb_debugfs_read()
669 				u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);  in ndev_ntb_debugfs_read()
675 			u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET);  in ndev_ntb_debugfs_read()
689 				u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET);  in ndev_ntb_debugfs_read()
698 			u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET);  in ndev_ntb_debugfs_read()
702 			u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET);  in ndev_ntb_debugfs_read()
714 				u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET);  in ndev_ntb_debugfs_read()
883 		base = ioread64(mmio + base_reg) & NTB_BAR_MASK_64;  in intel_ntb_mw_set_trans()
893 		reg_val = ioread64(mmio + xlat_reg);  in intel_ntb_mw_set_trans()
901 		reg_val = ioread64(mmio + limit_reg);  in intel_ntb_mw_set_trans()
1413 	bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);  in xeon_setup_b2b_mw()
1420 		bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);  in xeon_setup_b2b_mw()
1440 	bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);  in xeon_setup_b2b_mw()
1447 		bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);  in xeon_setup_b2b_mw()
1485 	bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);  in xeon_setup_b2b_mw()
1491 		bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);  in xeon_setup_b2b_mw()