Lines Matching defs:wl18xx_mac_and_phy_params
24 struct wl18xx_mac_and_phy_params { struct
25 u8 phy_standalone;
26 u8 spare0;
27 u8 enable_clpc;
28 u8 enable_tx_low_pwr_on_siso_rdl;
29 u8 auto_detect;
30 u8 dedicated_fem;
32 u8 low_band_component;
35 u8 low_band_component_type;
37 u8 high_band_component;
40 u8 high_band_component_type;
41 u8 number_of_assembled_ant2_4;
42 u8 number_of_assembled_ant5;
43 u8 pin_muxing_platform_options[PIN_MUXING_SIZE];
44 u8 external_pa_dc2dc;
45 u8 tcxo_ldo_voltage;
46 u8 xtal_itrim_val;
47 u8 srf_state;
48 u8 srf1[SRF_TABLE_LEN];
49 u8 srf2[SRF_TABLE_LEN];
50 u8 srf3[SRF_TABLE_LEN];
51 u8 io_configuration;
52 u8 sdio_configuration;
53 u8 settings;
54 u8 rx_profile;
55 u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG];
56 u8 pwr_limit_reference_11_abg;
57 u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P];
58 u8 pwr_limit_reference_11p;
59 u8 spare1;
60 u8 per_chan_bo_mode_11_abg[13];
61 u8 per_chan_bo_mode_11_p[4];
62 u8 primary_clock_setting_time;
63 u8 clock_valid_on_wake_up;
64 u8 secondary_clock_setting_time;
65 u8 board_type;
67 u8 psat;
69 s8 low_power_val;
70 s8 med_power_val;
71 s8 high_power_val;
72 s8 per_sub_band_tx_trace_loss[WL18XX_TRACE_LOSS_GAPS_TX];
73 s8 per_sub_band_rx_trace_loss[WL18XX_TRACE_LOSS_GAPS_RX];
74 u8 tx_rf_margin;
76 s8 low_power_val_2nd;
77 s8 med_power_val_2nd;
78 s8 high_power_val_2nd;
80 u8 padding[1];