realtek/rtw89/txrx.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
27 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_rate_mode()
40 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_ht_mcs()
48 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_mcs()
56 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_nss()
63 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
64 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
65 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
66 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
67 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
70 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
71 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
82 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
83 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
88 #define RTW89_TXWD_BODY3_BK BIT(13)
89 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
93 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
97 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
105 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
108 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
111 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
114 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
115 #define RTW89_TXWD_INFO0_DATA_ER BIT(15)
116 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
117 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8)
121 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
122 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
128 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
129 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
135 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
136 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
144 #define AX_RXD_BB_SEL BIT(22)
145 #define AX_RXD_MAC_INFO_VLD BIT(23)
146 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
148 #define AX_RXD_LONG_RXD BIT(31)
153 #define AX_RXD_SR_EN BIT(7)
156 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
158 #define AX_RXD_NON_SRG_PPDU BIT(28)
159 #define AX_RXD_INTER_PPDU BIT(29)
160 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
161 #define AX_RXD_INTER_PPDU_v1 BIT(15)
169 #define AX_RXD_A1_MATCH BIT(0)
170 #define AX_RXD_SW_DEC BIT(1)
171 #define AX_RXD_HW_DEC BIT(2)
172 #define AX_RXD_AMPDU BIT(3)
173 #define AX_RXD_AMPDU_END_PKT BIT(4)
174 #define AX_RXD_AMSDU BIT(5)
175 #define AX_RXD_AMSDU_CUT BIT(6)
176 #define AX_RXD_LAST_MSDU BIT(7)
177 #define AX_RXD_BYPASS BIT(8)
178 #define AX_RXD_CRC32_ERR BIT(9)
179 #define AX_RXD_ICV_ERR BIT(10)
180 #define AX_RXD_MAGIC_WAKE BIT(11)
181 #define AX_RXD_UNICAST_WAKE BIT(12)
182 #define AX_RXD_PATTERN_WAKE BIT(13)
186 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
187 #define AX_RXD_WITH_LLC BIT(25)
188 #define AX_RXD_RX_STATISTICS BIT(26)
192 #define AX_RXD_MC BIT(2)
193 #define AX_RXD_BC BIT(3)
194 #define AX_RXD_MD BIT(4)
195 #define AX_RXD_MF BIT(5)
196 #define AX_RXD_PWR BIT(6)
197 #define AX_RXD_QOS BIT(7)
199 #define AX_RXD_EOSP BIT(12)
200 #define AX_RXD_HTC BIT(13)
201 #define AX_RXD_QNULL BIT(14)
209 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
210 #define AX_RXD_ADDR_CAM_VLD BIT(28)
211 #define AX_RXD_ADDR_FWD_EN BIT(29)
212 #define AX_RXD_RX_PL_MATCH BIT(30)
219 #define AX_RXD_SMART_ANT BIT(16)
221 #define AX_RXD_HDR_CNV BIT(21)
223 #define AX_RXD_BIP_KEYID BIT(27)
224 #define AX_RXD_BIP_ENC BIT(28)
230 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
231 #define RTW89_RXINFO_USER_DATA BIT(1)
232 #define RTW89_RXINFO_USER_CTRL BIT(2)
233 #define RTW89_RXINFO_USER_MGMT BIT(3)
234 #define RTW89_RXINFO_USER_BCM BIT(4)
246 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
247 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
259 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
263 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
302 	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
311 	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1