Lines Matching refs:path
234 enum rtw89_rf_path path, bool is_bybb) in _rfk_rf_direct_cntrl() argument
237 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rfk_rf_direct_cntrl()
239 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rfk_rf_direct_cntrl()
243 enum rtw89_rf_path path, bool is_bybb) in _rfk_drf_direct_cntrl() argument
246 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _rfk_drf_direct_cntrl()
248 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _rfk_drf_direct_cntrl()
251 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path) in _iqk_check_cal() argument
268 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret); in _iqk_check_cal()
270 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8008 = 0x%x\n", path, val); in _iqk_check_cal()
294 enum rtw89_rf_path path) in _set_rx_dck() argument
296 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0); in _set_rx_dck()
297 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
298 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
304 u8 path, dck_tune; in _rx_dck() local
311 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _rx_dck()
312 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rx_dck()
313 dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE); in _rx_dck()
315 if (rtwdev->is_tssi_mode[path]) in _rx_dck()
317 R_P0_TSSI_TRK + (path << 13), in _rx_dck()
320 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
321 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
322 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rx_dck()
323 _set_rx_dck(rtwdev, phy, path); in _rx_dck()
324 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune); in _rx_dck()
325 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rx_dck()
327 if (rtwdev->is_tssi_mode[path]) in _rx_dck()
329 R_P0_TSSI_TRK + (path << 13), in _rx_dck()
334 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _rck() argument
341 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); in _rck()
343 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rck()
345 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
346 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rck()
349 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); in _rck()
352 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
355 false, rtwdev, path, RR_RCKS, BIT(3)); in _rck()
357 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); in _rck()
362 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); in _rck()
363 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rck()
366 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK)); in _rck()
486 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_addc() argument
492 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_addc()
506 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); in _check_addc()
586 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_dadc() argument
588 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
592 _check_addc(rtwdev, path); in _check_dadc()
594 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
790 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxk_setting() argument
795 switch (iqk_info->iqk_band[path]) { in _iqk_rxk_setting()
797 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_rxk_setting()
798 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_rxk_setting()
799 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_rxk_setting()
800 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _iqk_rxk_setting()
803 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_rxk_setting()
804 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_rxk_setting()
805 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_rxk_setting()
806 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _iqk_rxk_setting()
814 u8 path, u8 ktype) in _iqk_one_shot() argument
823 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
827 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
831 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
835 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
836 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
839 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
843 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
844 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
849 iqk_cmd = 0x408 | (1 << (4 + path)); in _iqk_one_shot()
854 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
862 fail = _iqk_check_cal(rtwdev, path); in _iqk_one_shot()
869 u8 path) in _rxk_group_sel() argument
877 switch (iqk_info->iqk_band[path]) { in _rxk_group_sel()
879 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _rxk_group_sel()
881 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, in _rxk_group_sel()
883 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, in _rxk_group_sel()
887 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _rxk_group_sel()
889 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT, in _rxk_group_sel()
891 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2, in _rxk_group_sel()
898 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _rxk_group_sel()
900 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _rxk_group_sel()
902 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _rxk_group_sel()
904 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); in _rxk_group_sel()
906 BIT(16 + gp + path * 4), fail); in _rxk_group_sel()
909 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _rxk_group_sel()
912 iqk_info->nb_rxcfir[path] = 0x40000002; in _rxk_group_sel()
913 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _rxk_group_sel()
915 iqk_info->is_wb_rxiqk[path] = false; in _rxk_group_sel()
917 iqk_info->nb_rxcfir[path] = 0x40000000; in _rxk_group_sel()
918 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _rxk_group_sel()
920 iqk_info->is_wb_rxiqk[path] = true; in _rxk_group_sel()
927 u8 path) in _iqk_nbrxk() argument
934 switch (iqk_info->iqk_band[path]) { in _iqk_nbrxk()
936 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _iqk_nbrxk()
938 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, in _iqk_nbrxk()
940 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, in _iqk_nbrxk()
944 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, in _iqk_nbrxk()
946 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT, in _iqk_nbrxk()
948 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2, in _iqk_nbrxk()
955 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_nbrxk()
956 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0); in _iqk_nbrxk()
957 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp); in _iqk_nbrxk()
958 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_nbrxk()
961 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK); in _iqk_nbrxk()
962 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail); in _iqk_nbrxk()
964 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _iqk_nbrxk()
967 iqk_info->nb_rxcfir[path] = in _iqk_nbrxk()
968 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD) | 0x2; in _iqk_nbrxk()
970 iqk_info->nb_rxcfir[path] = 0x40000002; in _iqk_nbrxk()
975 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxclk_setting() argument
979 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) { in _iqk_rxclk_setting()
1014 static bool _txk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _txk_group_sel() argument
1022 switch (iqk_info->iqk_band[path]) { in _txk_group_sel()
1024 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _txk_group_sel()
1026 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _txk_group_sel()
1028 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _txk_group_sel()
1030 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1034 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _txk_group_sel()
1036 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _txk_group_sel()
1038 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _txk_group_sel()
1040 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1047 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1049 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1051 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1053 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1056 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); in _txk_group_sel()
1058 BIT(8 + gp + path * 4), fail); in _txk_group_sel()
1063 iqk_info->nb_txcfir[path] = 0x40000002; in _txk_group_sel()
1064 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _txk_group_sel()
1066 iqk_info->is_wb_txiqk[path] = false; in _txk_group_sel()
1068 iqk_info->nb_txcfir[path] = 0x40000000; in _txk_group_sel()
1069 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _txk_group_sel()
1071 iqk_info->is_wb_txiqk[path] = true; in _txk_group_sel()
1077 static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_nbtxk() argument
1083 switch (iqk_info->iqk_band[path]) { in _iqk_nbtxk()
1085 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _iqk_nbtxk()
1087 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _iqk_nbtxk()
1089 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _iqk_nbtxk()
1091 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_nbtxk()
1095 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, in _iqk_nbtxk()
1097 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, in _iqk_nbtxk()
1099 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, in _iqk_nbtxk()
1101 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _iqk_nbtxk()
1108 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_nbtxk()
1109 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1); in _iqk_nbtxk()
1110 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0); in _iqk_nbtxk()
1111 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp); in _iqk_nbtxk()
1113 kfail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); in _iqk_nbtxk()
1116 iqk_info->nb_txcfir[path] = in _iqk_nbtxk()
1117 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), in _iqk_nbtxk()
1120 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_nbtxk()
1125 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias) in _lok_res_table() argument
1130 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias); in _lok_res_table()
1132 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); in _lok_res_table()
1133 if (iqk_info->iqk_band[path] == RTW89_BAND_2G) in _lok_res_table()
1134 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); in _lok_res_table()
1136 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); in _lok_res_table()
1137 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias); in _lok_res_table()
1138 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); in _lok_res_table()
1139 rtw89_write_rf(rtwdev, path, RR_TXVBUF, RR_TXVBUF_DACEN, 0x1); in _lok_res_table()
1141 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x7c = %x\n", path, in _lok_res_table()
1142 rtw89_read_rf(rtwdev, path, RR_TXVBUF, RFREG_MASK)); in _lok_res_table()
1145 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path) in _lok_finetune_check() argument
1156 tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK); in _lok_finetune_check()
1166 iqk_info->lok_idac[ch][path] = tmp; in _lok_finetune_check()
1168 tmp = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK); in _lok_finetune_check()
1177 iqk_info->lok_vbuf[ch][path] = tmp; in _lok_finetune_check()
1180 "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path, in _lok_finetune_check()
1181 iqk_info->lok_idac[ch][path]); in _lok_finetune_check()
1183 "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path, in _lok_finetune_check()
1184 iqk_info->lok_vbuf[ch][path]); in _lok_finetune_check()
1189 static bool _iqk_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_lok() argument
1196 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1198 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_lok()
1199 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6); in _iqk_lok()
1202 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_lok()
1203 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4); in _iqk_lok()
1209 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1211 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1214 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1220 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9); in _iqk_lok()
1221 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE); in _iqk_lok()
1222 iqk_info->lok_cor_fail[0][path] = tmp; in _iqk_lok()
1224 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1226 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1229 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1235 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24); in _iqk_lok()
1236 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER); in _iqk_lok()
1238 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1240 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1243 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1249 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9); in _iqk_lok()
1251 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE); in _iqk_lok()
1252 iqk_info->lok_fin_fail[0][path] = tmp; in _iqk_lok()
1254 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1256 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1259 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1265 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24); in _iqk_lok()
1266 _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER); in _iqk_lok()
1268 return _lok_finetune_check(rtwdev, path); in _iqk_lok()
1271 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txk_setting() argument
1275 switch (iqk_info->iqk_band[path]) { in _iqk_txk_setting()
1277 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW2, 0x00); in _iqk_txk_setting()
1278 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1279 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0); in _iqk_txk_setting()
1280 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1281 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1282 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1283 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00); in _iqk_txk_setting()
1284 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1288 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); in _iqk_txk_setting()
1289 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1); in _iqk_txk_setting()
1290 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1291 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1292 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80); in _iqk_txk_setting()
1293 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1301 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txclk_setting() argument
1314 static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_info_iqk() argument
1320 flag = iqk_info->lok_cor_fail[0][path]; in _iqk_info_iqk()
1321 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag); in _iqk_info_iqk()
1322 flag = iqk_info->lok_fin_fail[0][path]; in _iqk_info_iqk()
1323 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag); in _iqk_info_iqk()
1324 flag = iqk_info->iqk_tx_fail[0][path]; in _iqk_info_iqk()
1325 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag); in _iqk_info_iqk()
1326 flag = iqk_info->iqk_rx_fail[0][path]; in _iqk_info_iqk()
1327 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag); in _iqk_info_iqk()
1329 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD); in _iqk_info_iqk()
1330 iqk_info->bp_iqkenable[path] = tmp; in _iqk_info_iqk()
1331 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1332 iqk_info->bp_txkresult[path] = tmp; in _iqk_info_iqk()
1333 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1334 iqk_info->bp_rxkresult[path] = tmp; in _iqk_info_iqk()
1338 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4)); in _iqk_info_iqk()
1341 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4), in _iqk_info_iqk()
1345 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_by_path() argument
1353 _iqk_txclk_setting(rtwdev, path); in _iqk_by_path()
1357 _lok_res_table(rtwdev, path, ibias++); in _iqk_by_path()
1358 _iqk_txk_setting(rtwdev, path); in _iqk_by_path()
1359 lok_is_fail = _iqk_lok(rtwdev, phy_idx, path); in _iqk_by_path()
1365 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] LOK (%d) fail\n", path); in _iqk_by_path()
1369 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); in _iqk_by_path()
1371 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1374 _iqk_rxclk_setting(rtwdev, path); in _iqk_by_path()
1375 _iqk_rxk_setting(rtwdev, path); in _iqk_by_path()
1377 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); in _iqk_by_path()
1379 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1381 _iqk_info_iqk(rtwdev, phy_idx, path); in _iqk_by_path()
1384 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path) in _iqk_get_ch_info() argument
1394 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1402 idx = iqk_info->iqk_table_idx[path] + 1; in _iqk_get_ch_info()
1408 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_get_ch_info()
1411 iqk_info->iqk_band[path] = chan->band_type; in _iqk_get_ch_info()
1412 iqk_info->iqk_bw[path] = chan->band_width; in _iqk_get_ch_info()
1413 iqk_info->iqk_ch[path] = chan->channel; in _iqk_get_ch_info()
1414 iqk_info->iqk_mcc_ch[idx][path] = chan->channel; in _iqk_get_ch_info()
1415 iqk_info->iqk_table_idx[path] = idx; in _iqk_get_ch_info()
1418 path, reg_rf18, idx); in _iqk_get_ch_info()
1420 path, reg_rf18); in _iqk_get_ch_info()
1424 idx, path, iqk_info->iqk_mcc_ch[idx][path]); in _iqk_get_ch_info()
1432 "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path, in _iqk_get_ch_info()
1437 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16), in _iqk_get_ch_info()
1438 iqk_info->iqk_band[path]); in _iqk_get_ch_info()
1440 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16), in _iqk_get_ch_info()
1441 iqk_info->iqk_bw[path]); in _iqk_get_ch_info()
1442 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16), in _iqk_get_ch_info()
1443 iqk_info->iqk_ch[path]); in _iqk_get_ch_info()
1446 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_start_iqk() argument
1448 _iqk_by_path(rtwdev, phy_idx, path); in _iqk_start_iqk()
1451 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) in _iqk_restore() argument
1456 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1457 iqk_info->nb_txcfir[path]); in _iqk_restore()
1458 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1459 iqk_info->nb_rxcfir[path]); in _iqk_restore()
1461 0x00000e19 + (path << 4)); in _iqk_restore()
1462 fail = _iqk_check_cal(rtwdev, path); in _iqk_restore()
1472 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1473 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1474 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3); in _iqk_restore()
1475 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1476 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _iqk_restore()
1480 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_afebb_restore() argument
1505 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) in _iqk_preset() argument
1510 idx = iqk_info->iqk_table_idx[path]; in _iqk_preset()
1513 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx); in _iqk_preset()
1514 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx); in _iqk_preset()
1516 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1517 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _iqk_preset()
1521 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path, in _iqk_preset()
1522 rtw89_phy_read32_mask(rtwdev, R_CFIR_LUT + (path << 8), MASKDWORD)); in _iqk_preset()
1523 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path, in _iqk_preset()
1524 rtw89_phy_read32_mask(rtwdev, R_COEF_SEL + (path << 8), MASKDWORD)); in _iqk_preset()
1528 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_macbb_setting() argument
1554 u8 idx, path; in _iqk_init() local
1571 for (path = 0; path < RTW8852B_IQK_SS; path++) { in _iqk_init()
1572 iqk_info->lok_cor_fail[idx][path] = false; in _iqk_init()
1573 iqk_info->lok_fin_fail[idx][path] = false; in _iqk_init()
1574 iqk_info->iqk_tx_fail[idx][path] = false; in _iqk_init()
1575 iqk_info->iqk_rx_fail[idx][path] = false; in _iqk_init()
1576 iqk_info->iqk_mcc_ch[idx][path] = 0x0; in _iqk_init()
1577 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1585 u8 path; in _wait_rx_mode() local
1588 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
1589 if (!(kpath & BIT(path))) in _wait_rx_mode()
1594 rtwdev, path, RR_MOD, RR_MOD_MASK); in _wait_rx_mode()
1596 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret); in _wait_rx_mode()
1610 enum rtw89_phy_idx phy_idx, u8 path) in _doiqk() argument
1625 _iqk_get_ch_info(rtwdev, phy_idx, path); in _doiqk()
1628 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1629 _iqk_macbb_setting(rtwdev, phy_idx, path); in _doiqk()
1630 _iqk_preset(rtwdev, path); in _doiqk()
1631 _iqk_start_iqk(rtwdev, phy_idx, path); in _doiqk()
1632 _iqk_restore(rtwdev, path); in _doiqk()
1633 _iqk_afebb_restore(rtwdev, phy_idx, path); in _doiqk()
1635 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1661 u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path) in _dpk_bkup_kip() argument
1666 reg_bkup[path][i] = in _dpk_bkup_kip()
1667 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD); in _dpk_bkup_kip()
1669 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_bkup_kip()
1674 const u32 reg_bkup[][RTW8852B_DPK_KIP_REG_NUM], u8 path) in _dpk_reload_kip() argument
1679 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD, in _dpk_reload_kip()
1680 reg_bkup[path][i]); in _dpk_reload_kip()
1682 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_reload_kip()
1699 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off) in _dpk_onoff() argument
1702 u8 val, kidx = dpk->cur_idx[path]; in _dpk_onoff()
1704 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; in _dpk_onoff()
1706 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_onoff()
1709 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, in _dpk_onoff()
1714 enum rtw89_rf_path path, enum rtw8852b_dpk_id id) in _dpk_one_shot() argument
1720 dpk_cmd = (id << 8) | (0x19 + (path << 4)); in _dpk_one_shot()
1756 enum rtw89_rf_path path) in _dpk_rx_dck() argument
1758 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); in _dpk_rx_dck()
1759 _set_rx_dck(rtwdev, phy, path); in _dpk_rx_dck()
1763 enum rtw89_rf_path path) in _dpk_information() argument
1768 u8 kidx = dpk->cur_idx[path]; in _dpk_information()
1770 dpk->bp[path][kidx].band = chan->band_type; in _dpk_information()
1771 dpk->bp[path][kidx].ch = chan->channel; in _dpk_information()
1772 dpk->bp[path][kidx].bw = chan->band_width; in _dpk_information()
1776 path, dpk->cur_idx[path], phy, in _dpk_information()
1777 rtwdev->is_tssi_mode[path] ? "on" : "off", in _dpk_information()
1779 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1780 dpk->bp[path][kidx].band == 1 ? "5G" : "6G", in _dpk_information()
1781 dpk->bp[path][kidx].ch, in _dpk_information()
1782 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1783 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); in _dpk_information()
1788 enum rtw89_rf_path path, u8 kpath) in _dpk_bb_afe_setting() argument
1805 enum rtw89_rf_path path, u8 kpath) in _dpk_bb_afe_restore() argument
1821 enum rtw89_rf_path path, bool is_pause) in _dpk_tssi_pause() argument
1823 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), in _dpk_tssi_pause()
1826 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, in _dpk_tssi_pause()
1831 enum rtw89_rf_path path) in _dpk_kip_restore() argument
1836 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), B_DPD_COM_OF, 0x1); in _dpk_kip_restore()
1838 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); in _dpk_kip_restore()
1842 enum rtw89_rf_path path) in _dpk_lbk_rxiqk() argument
1847 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB); in _dpk_lbk_rxiqk()
1850 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0); in _dpk_lbk_rxiqk()
1852 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _dpk_lbk_rxiqk()
1853 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _dpk_lbk_rxiqk()
1854 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd); in _dpk_lbk_rxiqk()
1855 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
1858 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13); in _dpk_lbk_rxiqk()
1860 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00); in _dpk_lbk_rxiqk()
1862 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05); in _dpk_lbk_rxiqk()
1864 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0); in _dpk_lbk_rxiqk()
1865 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
1866 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014); in _dpk_lbk_rxiqk()
1872 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK); in _dpk_lbk_rxiqk()
1874 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, in _dpk_lbk_rxiqk()
1878 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
1881 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1); in _dpk_lbk_rxiqk()
1882 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5); in _dpk_lbk_rxiqk()
1885 static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path) in _dpk_get_thermal() argument
1889 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _dpk_get_thermal()
1890 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0); in _dpk_get_thermal()
1891 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _dpk_get_thermal()
1895 dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL); in _dpk_get_thermal()
1898 dpk->bp[path][kidx].ther_dpk); in _dpk_get_thermal()
1902 enum rtw89_rf_path path, u8 kidx) in _dpk_rf_setting() argument
1906 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { in _dpk_rf_setting()
1907 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1908 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2); in _dpk_rf_setting()
1909 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1910 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1912 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1913 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5); in _dpk_rf_setting()
1914 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1915 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1916 rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC); in _dpk_rf_setting()
1917 rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0); in _dpk_rf_setting()
1918 rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800); in _dpk_rf_setting()
1921 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
1922 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1); in _dpk_rf_setting()
1923 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
1927 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK), in _dpk_rf_setting()
1928 rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK), in _dpk_rf_setting()
1929 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK)); in _dpk_rf_setting()
1933 enum rtw89_rf_path path, bool is_bypass) in _dpk_bypass_rxcfir() argument
1936 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1938 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1941 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, in _dpk_bypass_rxcfir()
1942 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1945 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2); in _dpk_bypass_rxcfir()
1946 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS); in _dpk_bypass_rxcfir()
1948 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, in _dpk_bypass_rxcfir()
1949 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
1955 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_tpg_sel() argument
1959 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) in _dpk_tpg_sel()
1961 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) in _dpk_tpg_sel()
1967 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : in _dpk_tpg_sel()
1968 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); in _dpk_tpg_sel()
1972 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_table_select() argument
1977 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val); in _dpk_table_select()
1983 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_sync_check() argument
1999 path, corr_idx, corr_val); in _dpk_sync_check()
2001 dpk->corr_idx[path][kidx] = corr_idx; in _dpk_sync_check()
2002 dpk->corr_val[path][kidx] = corr_val; in _dpk_sync_check()
2013 path, dc_i, dc_q); in _dpk_sync_check()
2015 dpk->dc_i[path][kidx] = dc_i; in _dpk_sync_check()
2016 dpk->dc_q[path][kidx] = dc_q; in _dpk_sync_check()
2026 enum rtw89_rf_path path, u8 kidx) in _dpk_sync() argument
2028 _dpk_one_shot(rtwdev, phy, path, SYNC); in _dpk_sync()
2030 return _dpk_sync_check(rtwdev, path, kidx); in _dpk_sync()
2103 enum rtw89_rf_path path, u8 kidx) in _dpk_gainloss() argument
2105 _dpk_table_select(rtwdev, path, kidx, 1); in _dpk_gainloss()
2106 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS); in _dpk_gainloss()
2110 enum rtw89_rf_path path, u8 kidx) in _dpk_kip_preset() argument
2112 _dpk_tpg_sel(rtwdev, path, kidx); in _dpk_kip_preset()
2113 _dpk_one_shot(rtwdev, phy, path, KIP_PRESET); in _dpk_kip_preset()
2117 enum rtw89_rf_path path) in _dpk_kip_pwr_clk_on() argument
2121 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_pwr_clk_on()
2127 enum rtw89_rf_path path, u8 txagc) in _dpk_kip_set_txagc() argument
2129 rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, txagc); in _dpk_kip_set_txagc()
2131 _dpk_one_shot(rtwdev, phy, path, DPK_TXAGC); in _dpk_kip_set_txagc()
2138 enum rtw89_rf_path path) in _dpk_kip_set_rxagc() argument
2142 tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _dpk_kip_set_rxagc()
2145 _dpk_one_shot(rtwdev, phy, path, DPK_RXAGC); in _dpk_kip_set_rxagc()
2152 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB)); in _dpk_kip_set_rxagc()
2156 enum rtw89_rf_path path, s8 gain_offset) in _dpk_set_offset() argument
2160 txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK); in _dpk_set_offset()
2169 _dpk_kip_set_txagc(rtwdev, phy, path, txagc); in _dpk_set_offset()
2218 enum rtw89_rf_path path, u8 kidx, u8 init_txagc, in _dpk_agc() argument
2234 if (_dpk_sync(rtwdev, phy, path, kidx)) { in _dpk_agc()
2249 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, in _dpk_agc()
2263 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB, in _dpk_agc()
2269 _dpk_bypass_rxcfir(rtwdev, path, true); in _dpk_agc()
2271 _dpk_lbk_rxiqk(rtwdev, phy, path); in _dpk_agc()
2282 _dpk_gainloss(rtwdev, phy, path, kidx); in _dpk_agc()
2300 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0x3); in _dpk_agc()
2312 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0xfe); in _dpk_agc()
2318 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_gl_idx); in _dpk_agc()
2365 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_idl_mpa() argument
2369 if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 && in _dpk_idl_mpa()
2370 dpk->bp[path][kidx].band == RTW89_BAND_5G) in _dpk_idl_mpa()
2375 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL); in _dpk_idl_mpa()
2379 enum rtw89_rf_path path, u8 kidx, u8 gain, u8 txagc) in _dpk_fill_result() argument
2385 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _dpk_fill_result()
2392 dpk->bp[path][kidx].txagc_dpk = txagc; in _dpk_fill_result()
2393 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8), in _dpk_fill_result()
2396 dpk->bp[path][kidx].pwsf = pwsf; in _dpk_fill_result()
2397 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_fill_result()
2400 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2401 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0); in _dpk_fill_result()
2403 dpk->bp[path][kidx].gs = gs; in _dpk_fill_result()
2405 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2408 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2411 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2413 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0); in _dpk_fill_result()
2418 enum rtw89_rf_path path) in _dpk_reload_check() argument
2429 if (cur_band != dpk->bp[path][idx].band || in _dpk_reload_check()
2430 cur_ch != dpk->bp[path][idx].ch) in _dpk_reload_check()
2433 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _dpk_reload_check()
2435 dpk->cur_idx[path] = idx; in _dpk_reload_check()
2438 "[DPK] reload S%d[%d] success\n", path, idx); in _dpk_reload_check()
2445 enum rtw89_rf_path path, u8 gain) in _dpk_main() argument
2448 u8 txagc = 0x38, kidx = dpk->cur_idx[path]; in _dpk_main()
2452 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx); in _dpk_main()
2454 _rfk_rf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2455 _rfk_drf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2457 _dpk_kip_pwr_clk_on(rtwdev, path); in _dpk_main()
2458 _dpk_kip_set_txagc(rtwdev, phy, path, txagc); in _dpk_main()
2459 _dpk_rf_setting(rtwdev, gain, path, kidx); in _dpk_main()
2460 _dpk_rx_dck(rtwdev, phy, path); in _dpk_main()
2462 _dpk_kip_preset(rtwdev, phy, path, kidx); in _dpk_main()
2463 _dpk_kip_set_rxagc(rtwdev, phy, path); in _dpk_main()
2464 _dpk_table_select(rtwdev, path, kidx, gain); in _dpk_main()
2466 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false); in _dpk_main()
2472 _dpk_get_thermal(rtwdev, kidx, path); in _dpk_main()
2474 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain); in _dpk_main()
2476 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _dpk_main()
2478 _dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc); in _dpk_main()
2482 dpk->bp[path][kidx].path_ok = true; in _dpk_main()
2484 dpk->bp[path][kidx].path_ok = false; in _dpk_main()
2486 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, in _dpk_main()
2501 u8 path; in _dpk_cal_select() local
2504 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2505 reloaded[path] = _dpk_reload_check(rtwdev, phy, path); in _dpk_cal_select()
2506 if (!reloaded[path] && dpk->bp[path][0].ch) in _dpk_cal_select()
2507 dpk->cur_idx[path] = !dpk->cur_idx[path]; in _dpk_cal_select()
2509 _dpk_onoff(rtwdev, path, false); in _dpk_cal_select()
2512 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) in _dpk_cal_select()
2513 dpk->cur_idx[path] = 0; in _dpk_cal_select()
2518 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2519 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2520 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2521 _dpk_information(rtwdev, phy, path); in _dpk_cal_select()
2522 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2523 _dpk_tssi_pause(rtwdev, path, true); in _dpk_cal_select()
2526 _dpk_bb_afe_setting(rtwdev, phy, path, kpath); in _dpk_cal_select()
2528 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2529 is_fail = _dpk_main(rtwdev, phy, path, 1); in _dpk_cal_select()
2530 _dpk_onoff(rtwdev, path, is_fail); in _dpk_cal_select()
2533 _dpk_bb_afe_restore(rtwdev, phy, path, kpath); in _dpk_cal_select()
2536 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2537 _dpk_kip_restore(rtwdev, path); in _dpk_cal_select()
2538 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2539 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2540 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2541 _dpk_tssi_pause(rtwdev, path, false); in _dpk_cal_select()
2569 u8 path, kpath; in _dpk_force_bypass() local
2573 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_force_bypass()
2574 if (kpath & BIT(path)) in _dpk_force_bypass()
2575 _dpk_onoff(rtwdev, path, true); in _dpk_force_bypass()
2598 u8 path, kidx; in _dpk_track() local
2603 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _dpk_track()
2604 kidx = dpk->cur_idx[path]; in _dpk_track()
2608 path, kidx, dpk->bp[path][kidx].ch); in _dpk_track()
2610 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _dpk_track()
2615 if (dpk->bp[path][kidx].ch && cur_ther) in _dpk_track()
2616 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; in _dpk_track()
2618 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) in _dpk_track()
2619 delta_ther[path] = delta_ther[path] * 3 / 2; in _dpk_track()
2621 delta_ther[path] = delta_ther[path] * 5 / 2; in _dpk_track()
2623 txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2626 if (rtwdev->is_tssi_mode[path]) { in _dpk_track()
2627 trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK); in _dpk_track()
2634 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2637 rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13), in _dpk_track()
2645 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2650 txagc_ofst, delta_ther[path]); in _dpk_track()
2651 tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8), in _dpk_track()
2660 ini_diff = txagc_ofst + (delta_ther[path]); in _dpk_track()
2663 R_P0_TXDPD + (path << 13), in _dpk_track()
2666 pwsf[0] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2668 pwsf[1] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2671 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2672 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2676 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2677 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2687 R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2690 R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2699 u8 tx_scale, ofdm_bkof, path, kpath; in _set_dpd_backoff() local
2709 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _set_dpd_backoff()
2710 if (!(kpath & BIT(path))) in _set_dpd_backoff()
2713 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8), in _set_dpd_backoff()
2716 "[RFK] Set S%d DPD backoff to 0dB\n", path); in _set_dpd_backoff()
2724 enum rtw89_rf_path path) in _tssi_rf_setting() argument
2730 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2732 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2736 enum rtw89_rf_path path) in _tssi_set_sys() argument
2743 if (path == RF_PATH_A) in _tssi_set_sys()
2755 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb() argument
2757 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb()
2764 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb_he_tb() argument
2766 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb_he_tb()
2772 enum rtw89_rf_path path) in _tssi_set_dck() argument
2774 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dck()
2780 enum rtw89_rf_path path) in _tssi_set_tmeter_tbl() argument
2834 if (path == RF_PATH_A) { in _tssi_set_tmeter_tbl()
2938 enum rtw89_rf_path path) in _tssi_set_dac_gain_tbl() argument
2940 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dac_gain_tbl()
2946 enum rtw89_rf_path path) in _tssi_slope_cal_org() argument
2951 if (path == RF_PATH_A) in _tssi_slope_cal_org()
2962 enum rtw89_rf_path path, bool all) in _tssi_alignment_default() argument
2969 if (path == RF_PATH_A) { in _tssi_alignment_default()
3020 enum rtw89_rf_path path) in _tssi_set_tssi_slope() argument
3022 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_tssi_slope()
3028 enum rtw89_rf_path path) in _tssi_set_tssi_track() argument
3030 if (path == RF_PATH_A) in _tssi_set_tssi_track()
3038 enum rtw89_rf_path path) in _tssi_set_txagc_offset_mv_avg() argument
3041 path); in _tssi_set_txagc_offset_mv_avg()
3043 if (path == RF_PATH_A) in _tssi_set_txagc_offset_mv_avg()
3233 enum rtw89_rf_path path) in _tssi_get_ofdm_de() argument
3246 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx); in _tssi_get_ofdm_de()
3251 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; in _tssi_get_ofdm_de()
3252 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; in _tssi_get_ofdm_de()
3257 path, val, de_1st, de_2nd); in _tssi_get_ofdm_de()
3259 val = tssi_info->tssi_mcs[path][gidx]; in _tssi_get_ofdm_de()
3262 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); in _tssi_get_ofdm_de()
3269 enum rtw89_rf_path path) in _tssi_get_ofdm_trim_de() argument
3283 path, tgidx); in _tssi_get_ofdm_trim_de()
3288 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; in _tssi_get_ofdm_trim_de()
3289 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; in _tssi_get_ofdm_trim_de()
3294 path, val, tde_1st, tde_2nd); in _tssi_get_ofdm_trim_de()
3296 val = tssi_info->tssi_trim[path][tgidx]; in _tssi_get_ofdm_trim_de()
3300 path, val); in _tssi_get_ofdm_trim_de()
3361 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _tssi_alimentk_dump_result() argument
3366 R_TSSI_PA_K1 + (path << 13), in _tssi_alimentk_dump_result()
3367 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3368 R_TSSI_PA_K2 + (path << 13), in _tssi_alimentk_dump_result()
3369 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3370 R_P0_TSSI_ALIM1 + (path << 13), in _tssi_alimentk_dump_result()
3371 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3372 R_P0_TSSI_ALIM3 + (path << 13), in _tssi_alimentk_dump_result()
3373 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3374 R_TSSI_PA_K5 + (path << 13), in _tssi_alimentk_dump_result()
3375 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3376 R_P0_TSSI_ALIM2 + (path << 13), in _tssi_alimentk_dump_result()
3377 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3378 R_P0_TSSI_ALIM4 + (path << 13), in _tssi_alimentk_dump_result()
3379 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD), in _tssi_alimentk_dump_result()
3380 R_TSSI_PA_K8 + (path << 13), in _tssi_alimentk_dump_result()
3381 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD)); in _tssi_alimentk_dump_result()
3385 enum rtw89_phy_idx phy, enum rtw89_rf_path path) in _tssi_alimentk_done() argument
3393 "======>%s phy=%d path=%d\n", __func__, phy, path); in _tssi_alimentk_done()
3406 if (tssi_info->alignment_done[path][band]) { in _tssi_alimentk_done()
3407 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3408 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk_done()
3409 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3410 tssi_info->alignment_value[path][band][1]); in _tssi_alimentk_done()
3411 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3412 tssi_info->alignment_value[path][band][2]); in _tssi_alimentk_done()
3413 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD, in _tssi_alimentk_done()
3414 tssi_info->alignment_value[path][band][3]); in _tssi_alimentk_done()
3417 _tssi_alimentk_dump_result(rtwdev, path); in _tssi_alimentk_done()
3421 enum rtw89_rf_path path, u16 cnt, u16 period, s16 pwr_dbm, in _tssi_hw_tx() argument
3426 if (path == RF_PATH_A) in _tssi_hw_tx()
3428 else if (path == RF_PATH_B) in _tssi_hw_tx()
3430 else if (path == RF_PATH_AB) in _tssi_hw_tx()
3437 rtw8852b_bb_cfg_tx_path(rtwdev, path); in _tssi_hw_tx()
3495 enum rtw89_rf_path path, const s16 *power, in _tssi_get_cw_report() argument
3504 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0); in _tssi_get_cw_report()
3505 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1); in _tssi_get_cw_report()
3509 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD); in _tssi_get_cw_report()
3512 _tssi_trigger[path], tmp, path); in _tssi_get_cw_report()
3515 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true); in _tssi_get_cw_report()
3524 tx_counter_tmp, path); in _tssi_get_cw_report()
3527 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], in _tssi_get_cw_report()
3540 k, tx_counter_tmp, path); in _tssi_get_cw_report()
3546 k, path); in _tssi_get_cw_report()
3548 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false); in _tssi_get_cw_report()
3553 rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], B_TSSI_CWRPT); in _tssi_get_cw_report()
3555 _tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false); in _tssi_get_cw_report()
3562 tx_counter_tmp, path); in _tssi_get_cw_report()
3569 enum rtw89_rf_path path) in _tssi_alimentk() argument
3593 path); in _tssi_alimentk()
3595 if (tssi_info->check_backup_aligmk[path][ch_idx]) { in _tssi_alimentk()
3596 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD, in _tssi_alimentk()
3597 tssi_info->alignment_backup_by_ch[path][ch_idx][0]); in _tssi_alimentk()
3598 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD, in _tssi_alimentk()
3599 tssi_info->alignment_backup_by_ch[path][ch_idx][1]); in _tssi_alimentk()
3600 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD, in _tssi_alimentk()
3601 tssi_info->alignment_backup_by_ch[path][ch_idx][2]); in _tssi_alimentk()
3602 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD, in _tssi_alimentk()
3603 tssi_info->alignment_backup_by_ch[path][ch_idx][3]); in _tssi_alimentk()
3607 _tssi_alimentk_dump_result(rtwdev, path); in _tssi_alimentk()
3637 ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt); in _tssi_alimentk()
3647 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1], in _tssi_alimentk()
3654 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2], in _tssi_alimentk()
3659 tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3], in _tssi_alimentk()
3664 if (path == RF_PATH_A) { in _tssi_alimentk()
3694 tssi_info->alignment_done[path][band] = true; in _tssi_alimentk()
3695 tssi_info->alignment_value[path][band][0] = in _tssi_alimentk()
3696 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD); in _tssi_alimentk()
3697 tssi_info->alignment_value[path][band][1] = in _tssi_alimentk()
3698 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD); in _tssi_alimentk()
3699 tssi_info->alignment_value[path][band][2] = in _tssi_alimentk()
3700 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD); in _tssi_alimentk()
3701 tssi_info->alignment_value[path][band][3] = in _tssi_alimentk()
3702 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD); in _tssi_alimentk()
3704 tssi_info->check_backup_aligmk[path][ch_idx] = true; in _tssi_alimentk()
3705 tssi_info->alignment_backup_by_ch[path][ch_idx][0] = in _tssi_alimentk()
3706 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD); in _tssi_alimentk()
3707 tssi_info->alignment_backup_by_ch[path][ch_idx][1] = in _tssi_alimentk()
3708 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD); in _tssi_alimentk()
3709 tssi_info->alignment_backup_by_ch[path][ch_idx][2] = in _tssi_alimentk()
3710 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD); in _tssi_alimentk()
3711 tssi_info->alignment_backup_by_ch[path][ch_idx][3] = in _tssi_alimentk()
3712 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD); in _tssi_alimentk()
3716 path, band, R_P0_TSSI_ALIM1 + (path << 13), in _tssi_alimentk()
3717 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk()
3720 path, band, R_P0_TSSI_ALIM3 + (path << 13), in _tssi_alimentk()
3721 tssi_info->alignment_value[path][band][1]); in _tssi_alimentk()
3724 path, band, R_P0_TSSI_ALIM2 + (path << 13), in _tssi_alimentk()
3725 tssi_info->alignment_value[path][band][2]); in _tssi_alimentk()
3728 path, band, R_P0_TSSI_ALIM4 + (path << 13), in _tssi_alimentk()
3729 tssi_info->alignment_value[path][band][3]); in _tssi_alimentk()
3751 u8 path; in rtw8852b_rck() local
3753 for (path = 0; path < RF_PATH_NUM_8852B; path++) in rtw8852b_rck()
3754 _rck(rtwdev, path); in rtw8852b_rck()
3945 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, in _bw_setting() argument
3953 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK); in _bw_setting()
3956 "[RFK]Invalid RF_0x18 for Path-%d\n", path); in _bw_setting()
3980 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18); in _bw_setting()
3983 bw, path, reg18_addr, in _bw_setting()
3984 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK)); in _bw_setting()
4073 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, in _ch_setting() argument
4082 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK); in _ch_setting()
4095 if (path == RF_PATH_A && dav) in _ch_setting()
4098 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18); in _ch_setting()
4100 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0); in _ch_setting()
4101 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1); in _ch_setting()
4105 central_ch, path, reg18_addr, in _ch_setting()
4106 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK)); in _ch_setting()
4118 enum rtw89_rf_path path) in _set_rxbb_bw() argument
4120 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1); in _set_rxbb_bw()
4121 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12); in _set_rxbb_bw()
4124 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b); in _set_rxbb_bw()
4126 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13); in _set_rxbb_bw()
4128 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb); in _set_rxbb_bw()
4130 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3); in _set_rxbb_bw()
4132 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path, in _set_rxbb_bw()
4133 rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB)); in _set_rxbb_bw()
4135 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0); in _set_rxbb_bw()
4141 u8 kpath, path; in _rxbb_bw() local
4145 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _rxbb_bw()
4146 if (!(kpath & BIT(path))) in _rxbb_bw()
4149 _set_rxbb_bw(rtwdev, bw, path); in _rxbb_bw()