Lines Matching +full:0 +full:x80e8

8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
11 #define R_AX_SYS_ISO_CTRL 0x0000
17 #define R_AX_SYS_FUNC_EN 0x0002
19 #define B_AX_FEN_BBRSTB BIT(0)
21 #define R_AX_SYS_PW_CTRL 0x0004
36 #define R_AX_SYS_CLK_CTRL 0x0008
39 #define R_AX_SYS_SWR_CTRL1 0x0010
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
46 #define R_AX_RSV_CTRL 0x001C
50 #define R_AX_AFE_LDO_CTRL 0x0020
53 #define R_AX_EFUSE_CTRL_1 0x0038
62 #define R_AX_EFUSE_CTRL 0x0030
67 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
69 #define R_AX_EFUSE_CTRL_1_V1 0x0038
80 #define R_AX_GPIO_MUXCFG 0x0040
93 #define MAC_AX_BT_MODE_0_3 0
95 #define MAC_AX_RTK_MODE 0
100 #define B_AX_GPIOSEL_MASK GENMASK(1, 0)
102 #define R_AX_DBG_CTRL 0x0058
108 #define B_AX_DBG_SEL0 GENMASK(7, 0)
110 #define R_AX_SYS_SDIO_CTRL 0x0070
118 #define R_AX_HCI_OPT_CTRL 0x0074
121 #define R_AX_HCI_BG_CTRL 0x0078
127 #define B_AX_R_AX_BG GENMASK(1, 0)
129 #define R_AX_HCI_LDO_CTRL 0x007A
130 #define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
132 #define R_AX_PLATFORM_ENABLE 0x0088
136 #define B_AX_PLATFORM_EN BIT(0)
138 #define R_AX_WLLPS_CTRL 0x0090
142 #define SW_LPS_OPTION 0x0001A0B2
144 #define R_AX_SCOREBOARD  0x00AC
147 #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
148 #define B_MAC_AX_BTGS1_NOTIFY BIT(0)
149 #define MAC_AX_NOTIFY_TP_MAJOR 0x81
150 #define MAC_AX_NOTIFY_PWR_MAJOR 0x80
152 #define R_AX_DBG_PORT_SEL 0x00C0
153 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
155 #define R_AX_PMC_DBG_CTRL2 0x00CC
158 #define R_AX_PCIE_MIO_INTF 0x00E4
163 #define MIO_WRITE_BYTE_ALL 0xF
164 #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
167 #define R_AX_PCIE_MIO_INTD 0x00E8
168 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
170 #define R_AX_SYS_CFG1 0x00F0
173 #define R_AX_SYS_STATUS1 0x00F4
176 #define MAC_AX_HCI_SEL_SDIO_UART 0
182 #define R_AX_HALT_H2C_CTRL 0x0160
183 #define R_AX_HALT_H2C 0x0168
184 #define B_AX_HALT_H2C_TRIGGER BIT(0)
185 #define R_AX_HALT_C2H_CTRL 0x0164
186 #define R_AX_HALT_C2H 0x016C
188 #define R_AX_WCPU_FW_CTRL 0x01E0
192 #define B_AX_WCPU_FWDL_EN BIT(0)
194 #define R_AX_RPWM 0x01E4
195 #define R_AX_PCIE_HRPWM 0x10C0
200 #define PS_RPWM_STATE 0x7
204 #define PS_CPWM_STATE GENMASK(2, 0)
207 #define R_AX_BOOT_REASON 0x01E6
208 #define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
210 #define R_AX_LDM 0x01E8
213 #define R_AX_UDM0 0x01F0
214 #define R_AX_UDM1 0x01F4
219 #define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
220 #define R_AX_UDM2 0x01F8
221 #define R_AX_UDM3 0x01FC
223 #define R_AX_SPS_DIG_ON_CTRL0 0x0200
227 #define B_AX_VOL_L1_MASK GENMASK(3, 0)
229 #define R_AX_SPSLDO_ON_CTRL1 0x0204
232 #define R_AX_LDO_AON_CTRL0 0x0218
235 #define R_AX_SPSANA_ON_CTRL1 0x0224
237 #define R_AX_WLAN_XTAL_SI_CTRL 0x0270
243 #define XTAL_SI_NORMAL_WRITE 0x00
244 #define XTAL_SI_NORMAL_READ 0x01
247 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
249 #define R_AX_WLAN_XTAL_SI_CONFIG 0x0274
250 #define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0)
252 #define R_AX_XTAL_ON_CTRL0 0x0280
256 #define B_AX_XTAL_SC_MASK GENMASK(6, 0)
258 #define R_AX_XTAL_ON_CTRL3 0x028C
262 #define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0)
264 #define R_AX_GPIO0_7_FUNC_SEL 0x02D0
266 #define R_AX_EECS_EESK_FUNC_SEL 0x02D8
269 #define R_AX_GPIO16_23_FUNC_SEL 0x02D8
271 #define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0)
273 #define R_AX_LED1_FUNC_SEL 0x02DC
275 #define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
277 #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
282 #define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
286 #define R_AX_WLRF_CTRL 0x02F0
293 #define R_AX_IC_PWR_STATE 0x03F0
299 #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
301 #define R_AX_SPS_DIG_OFF_CTRL0 0x0400
303 #define B_AX_C1_L1_MASK GENMASK(1, 0)
305 #define R_AX_AFE_OFF_CTRL1 0x0444
310 #define R_AX_SEC_CTRL 0x0C00
313 #define R_AX_FILTER_MODEL_ADDR 0x0C04
315 #define R_AX_HAXI_INIT_CFG1 0x1000
319 #define DMA_MOD_PCIE_1B 0x0
320 #define DMA_MOD_PCIE_4B 0x1
321 #define DMA_MOD_USB 0x2
322 #define DMA_MOD_SDIO 0x3
331 #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
333 #define R_AX_HAXI_DMA_STOP1 0x1010
347 #define R_AX_HAXI_DMA_BUSY1 0x101C
362 #define R_AX_PCIE_DBG_CTRL 0x11C0
367 #define B_AX_EN_STUCK_DBG BIT(0)
369 #define R_AX_HAXI_DMA_STOP2 0x11C0
371 #define B_AX_STOP_CH10 BIT(0)
373 #define R_AX_HAXI_DMA_BUSY2 0x11C8
375 #define B_AX_CH10_BUSY BIT(0)
377 #define R_AX_HAXI_DMA_BUSY3 0x1208
379 #define B_AX_RXQ_BUSY BIT(0)
381 #define R_AX_LTR_DEC_CTRL 0x1600
394 #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
397 #define R_AX_LTR_LATENCY_IDX0 0x1604
398 #define R_AX_LTR_LATENCY_IDX1 0x1608
399 #define R_AX_LTR_LATENCY_IDX2 0x160C
400 #define R_AX_LTR_LATENCY_IDX3 0x1610
402 #define R_AX_HCI_FC_CTRL_V1 0x1700
403 #define R_AX_CH_PAGE_CTRL_V1 0x1704
405 #define R_AX_ACH0_PAGE_CTRL_V1 0x1710
406 #define R_AX_ACH1_PAGE_CTRL_V1 0x1714
407 #define R_AX_ACH2_PAGE_CTRL_V1 0x1718
408 #define R_AX_ACH3_PAGE_CTRL_V1 0x171C
409 #define R_AX_ACH4_PAGE_CTRL_V1 0x1720
410 #define R_AX_ACH5_PAGE_CTRL_V1 0x1724
411 #define R_AX_ACH6_PAGE_CTRL_V1 0x1728
412 #define R_AX_ACH7_PAGE_CTRL_V1 0x172C
413 #define R_AX_CH8_PAGE_CTRL_V1 0x1730
414 #define R_AX_CH9_PAGE_CTRL_V1 0x1734
415 #define R_AX_CH10_PAGE_CTRL_V1 0x1738
416 #define R_AX_CH11_PAGE_CTRL_V1 0x173C
418 #define R_AX_ACH0_PAGE_INFO_V1 0x1750
419 #define R_AX_ACH1_PAGE_INFO_V1 0x1754
420 #define R_AX_ACH2_PAGE_INFO_V1 0x1758
421 #define R_AX_ACH3_PAGE_INFO_V1 0x175C
422 #define R_AX_ACH4_PAGE_INFO_V1 0x1760
423 #define R_AX_ACH5_PAGE_INFO_V1 0x1764
424 #define R_AX_ACH6_PAGE_INFO_V1 0x1768
425 #define R_AX_ACH7_PAGE_INFO_V1 0x176C
426 #define R_AX_CH8_PAGE_INFO_V1 0x1770
427 #define R_AX_CH9_PAGE_INFO_V1 0x1774
428 #define R_AX_CH10_PAGE_INFO_V1 0x1778
429 #define R_AX_CH11_PAGE_INFO_V1 0x177C
430 #define R_AX_CH12_PAGE_INFO_V1 0x1780
432 #define R_AX_PUB_PAGE_INFO3_V1 0x178C
433 #define R_AX_PUB_PAGE_CTRL1_V1 0x1790
434 #define R_AX_PUB_PAGE_CTRL2_V1 0x1794
435 #define R_AX_PUB_PAGE_INFO1_V1 0x1798
436 #define R_AX_PUB_PAGE_INFO2_V1 0x179C
437 #define R_AX_WP_PAGE_CTRL1_V1 0x17A0
438 #define R_AX_WP_PAGE_CTRL2_V1 0x17A4
439 #define R_AX_WP_PAGE_INFO1_V1 0x17A8
441 #define R_AX_H2CREG_DATA0_V1 0x7140
442 #define R_AX_H2CREG_DATA1_V1 0x7144
443 #define R_AX_H2CREG_DATA2_V1 0x7148
444 #define R_AX_H2CREG_DATA3_V1 0x714C
445 #define R_AX_C2HREG_DATA0_V1 0x7150
446 #define R_AX_C2HREG_DATA1_V1 0x7154
447 #define R_AX_C2HREG_DATA2_V1 0x7158
448 #define R_AX_C2HREG_DATA3_V1 0x715C
449 #define R_AX_H2CREG_CTRL_V1 0x7160
450 #define R_AX_C2HREG_CTRL_V1 0x7164
452 #define R_AX_HCI_FUNC_EN_V1 0x7880
454 #define R_AX_PHYREG_SET 0x8040
455 #define PHYREG_SET_ALL_CYCLE 0x8
456 #define PHYREG_SET_XYN_CYCLE 0xE
458 #define R_AX_HD0IMR 0x8110
462 #define B_AX_C2H_INT_EN BIT(0)
463 #define R_AX_HD0ISR 0x8114
464 #define B_AX_C2H_INT BIT(0)
466 #define R_AX_H2CREG_DATA0 0x8140
467 #define R_AX_H2CREG_DATA1 0x8144
468 #define R_AX_H2CREG_DATA2 0x8148
469 #define R_AX_H2CREG_DATA3 0x814C
470 #define R_AX_C2HREG_DATA0 0x8150
471 #define R_AX_C2HREG_DATA1 0x8154
472 #define R_AX_C2HREG_DATA2 0x8158
473 #define R_AX_C2HREG_DATA3 0x815C
474 #define R_AX_H2CREG_CTRL 0x8160
475 #define B_AX_H2CREG_TRIGGER BIT(0)
476 #define R_AX_C2HREG_CTRL 0x8164
477 #define B_AX_C2HREG_TRIGGER BIT(0)
478 #define R_AX_CPWM 0x8170
480 #define R_AX_HCI_FUNC_EN 0x8380
482 #define B_AX_HCI_TXDMA_EN BIT(0)
484 #define R_AX_BOOT_DBG 0x83F0
486 #define R_AX_DMAC_FUNC_EN 0x8400
507 #define R_AX_DMAC_CLK_EN 0x8404
520 #define PCI_LTR_IDLE_TIMER_1US 0
528 #define PCI_LTR_IDLE_TIMER_R_ERR 0xFD
529 #define PCI_LTR_IDLE_TIMER_DEF 0xFE
530 #define PCI_LTR_IDLE_TIMER_IGNORE 0xFF
532 #define PCI_LTR_SPC_10US 0
536 #define PCI_LTR_SPC_R_ERR 0xFD
537 #define PCI_LTR_SPC_DEF 0xFE
538 #define PCI_LTR_SPC_IGNORE 0xFF
540 #define R_AX_LTR_CTRL_0 0x8410
548 #define B_AX_LTR_HW_EN BIT(0)
550 #define R_AX_LTR_CTRL_1 0x8414
552 #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
554 #define R_AX_LTR_IDLE_LATENCY 0x8418
556 #define R_AX_LTR_ACTIVE_LATENCY 0x841C
558 #define R_AX_SER_DBG_INFO 0x8424
561 #define R_AX_DLE_EMPTY0 0x8430
581 #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
583 #define R_AX_DLE_EMPTY1 0x8434
594 #define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0)
596 #define R_AX_DMAC_ERR_IMR 0x8520
607 #define B_AX_WDRLS_ERR_INT_EN BIT(0)
608 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
609 #define DMAC_ERR_IMR_DIS 0
611 #define R_AX_DMAC_ERR_ISR 0x8524
626 #define B_AX_WDRLS_ERR_FLAG BIT(0)
628 #define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800
631 #define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804
632 #define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808
633 #define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C
634 #define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810
635 #define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0)
637 #define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850
667 #define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0)
732 #define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
769 #define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854
798 #define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0)
858 #define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
894 #define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858
912 #define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
994 #define R_AX_DISPATCHER_DBG_PORT 0x8860
997 #define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0)
999 #define R_AX_RX_FUNCTION_STOP 0x8920
1000 #define B_AX_HDR_RX_STOP BIT(0)
1002 #define R_AX_HCI_FC_CTRL 0x8A00
1009 #define B_AX_HCI_FC_EN BIT(0)
1011 #define R_AX_CH_PAGE_CTRL 0x8A04
1013 #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
1016 #define B_AX_MIN_PG_MASK GENMASK(12, 0)
1018 #define R_AX_ACH0_PAGE_CTRL 0x8A10
1019 #define R_AX_ACH1_PAGE_CTRL 0x8A14
1020 #define R_AX_ACH2_PAGE_CTRL 0x8A18
1021 #define R_AX_ACH3_PAGE_CTRL 0x8A1C
1022 #define R_AX_ACH4_PAGE_CTRL 0x8A20
1023 #define R_AX_ACH5_PAGE_CTRL 0x8A24
1024 #define R_AX_ACH6_PAGE_CTRL 0x8A28
1025 #define R_AX_ACH7_PAGE_CTRL 0x8A2C
1026 #define R_AX_CH8_PAGE_CTRL 0x8A30
1027 #define R_AX_CH9_PAGE_CTRL 0x8A34
1028 #define R_AX_CH10_PAGE_CTRL 0x8A38
1029 #define R_AX_CH11_PAGE_CTRL 0x8A3C
1032 #define B_AX_USE_PG_MASK GENMASK(12, 0)
1033 #define R_AX_ACH0_PAGE_INFO 0x8A50
1034 #define R_AX_ACH1_PAGE_INFO 0x8A54
1035 #define R_AX_ACH2_PAGE_INFO 0x8A58
1036 #define R_AX_ACH3_PAGE_INFO 0x8A5C
1037 #define R_AX_ACH4_PAGE_INFO 0x8A60
1038 #define R_AX_ACH5_PAGE_INFO 0x8A64
1039 #define R_AX_ACH6_PAGE_INFO 0x8A68
1040 #define R_AX_ACH7_PAGE_INFO 0x8A6C
1041 #define R_AX_CH8_PAGE_INFO 0x8A70
1042 #define R_AX_CH9_PAGE_INFO 0x8A74
1043 #define R_AX_CH10_PAGE_INFO 0x8A78
1044 #define R_AX_CH11_PAGE_INFO 0x8A7C
1045 #define R_AX_CH12_PAGE_INFO 0x8A80
1047 #define R_AX_PUB_PAGE_INFO3 0x8A8C
1049 #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
1051 #define R_AX_PUB_PAGE_CTRL1 0x8A90
1053 #define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
1055 #define R_AX_PUB_PAGE_CTRL2 0x8A94
1056 #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
1058 #define R_AX_PUB_PAGE_INFO1 0x8A98
1060 #define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
1062 #define R_AX_PUB_PAGE_INFO2 0x8A9C
1063 #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
1065 #define R_AX_WP_PAGE_CTRL1 0x8AA0
1067 #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
1069 #define R_AX_WP_PAGE_CTRL2 0x8AA4
1070 #define B_AX_WP_THRD_MASK GENMASK(12, 0)
1072 #define R_AX_WP_PAGE_INFO1 0x8AA8
1075 #define R_AX_WDE_PKTBUF_CFG 0x8C08
1077 #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
1080 #define R_AX_WDE_ERRFLAG_MSG 0x8C30
1081 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1083 #define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34
1089 #define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0)
1091 #define R_AX_WDE_ERR_IMR 0x8C38
1111 #define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1221 #define R_AX_WDE_ERR_ISR 0x8C3C
1241 #define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0)
1244 #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
1245 #define R_AX_WDE_QTA0_CFG 0x8C40
1246 #define R_AX_WDE_QTA1_CFG 0x8C44
1247 #define R_AX_WDE_QTA2_CFG 0x8C48
1248 #define R_AX_WDE_QTA3_CFG 0x8C4C
1249 #define R_AX_WDE_QTA4_CFG 0x8C50
1251 #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
1252 #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
1255 #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
1256 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1258 #define R_AX_WDE_INI_STATUS 0x8D00
1260 #define B_AX_WDE_BUF_MGN_INI_RDY BIT(0)
1262 #define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10
1265 #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
1266 #define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14
1267 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1269 #define R_AX_PLE_PKTBUF_CFG 0x9008
1271 #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
1274 #define R_AX_PLE_DBGERR_LOCKEN 0x9020
1282 #define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0)
1284 #define R_AX_PLE_DBGERR_STS 0x9024
1292 #define B_AX_PLE_LOCKON_DLEPIF00 BIT(0)
1294 #define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034
1300 #define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0)
1302 #define R_AX_PLE_ERRFLAG_MSG 0x9030
1303 #define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1327 #define R_AX_PLE_ERR_IMR 0x9038
1347 #define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
1446 #define R_AX_PLE_ERR_FLAG_ISR 0x903C
1448 #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
1449 #define R_AX_PLE_QTA0_CFG 0x9040
1450 #define R_AX_PLE_QTA1_CFG 0x9044
1451 #define R_AX_PLE_QTA2_CFG 0x9048
1452 #define R_AX_PLE_QTA3_CFG 0x904C
1453 #define R_AX_PLE_QTA4_CFG 0x9050
1454 #define R_AX_PLE_QTA5_CFG 0x9054
1455 #define R_AX_PLE_QTA6_CFG 0x9058
1457 #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
1458 #define R_AX_PLE_QTA7_CFG 0x905C
1459 #define R_AX_PLE_QTA8_CFG 0x9060
1460 #define R_AX_PLE_QTA9_CFG 0x9064
1461 #define R_AX_PLE_QTA10_CFG 0x9068
1462 #define R_AX_PLE_QTA11_CFG 0x906C
1464 #define R_AX_PLE_INI_STATUS 0x9100
1466 #define B_AX_PLE_BUF_MGN_INI_RDY BIT(0)
1468 #define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110
1471 #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
1472 #define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114
1473 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1475 #define R_AX_WDRLS_CFG 0x9408
1477 #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
1479 #define R_AX_RLSRPT0_CFG0 0x9410
1483 #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
1485 #define R_AX_RLSRPT0_CFG1 0x9414
1487 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1489 #define R_AX_WDRLS_ERR_IMR 0x9430
1498 #define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
1526 #define R_AX_WDRLS_ERR_ISR 0x9434
1528 #define R_AX_BBRPT_COM_ERR_IMR 0x9608
1530 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1532 #define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C
1534 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
1536 #define R_AX_BBRPT_COM_ERR_ISR 0x960C
1537 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0)
1539 #define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C
1547 #define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0)
1549 #define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628
1557 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1567 #define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C
1583 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
1593 #define R_AX_BBRPT_DFS_ERR_IMR 0x9638
1594 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1596 #define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C
1598 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
1600 #define R_AX_BBRPT_DFS_ERR_ISR 0x963C
1601 #define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0)
1603 #define R_AX_LA_ERRFLAG 0x966C
1605 #define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
1607 #define R_AX_WD_BUF_REQ 0x9800
1608 #define R_AX_PL_BUF_REQ 0x9820
1611 #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
1613 #define R_AX_WD_BUF_STATUS 0x9804
1614 #define R_AX_PL_BUF_STATUS 0x9824
1616 #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
1617 #define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0)
1619 #define R_AX_WD_CPUQ_OP_0 0x9810
1620 #define R_AX_PL_CPUQ_OP_0 0x9830
1624 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1626 #define R_AX_WD_CPUQ_OP_1 0x9814
1627 #define R_AX_PL_CPUQ_OP_1 0x9834
1631 #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
1633 #define R_AX_WD_CPUQ_OP_2 0x9818
1634 #define R_AX_PL_CPUQ_OP_2 0x9838
1636 #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
1638 #define R_AX_WD_CPUQ_OP_STATUS 0x981C
1639 #define R_AX_PL_CPUQ_OP_STATUS 0x983C
1641 #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
1643 #define R_AX_CPUIO_ERR_IMR 0x9840
1647 #define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0)
1657 #define R_AX_CPUIO_ERR_ISR 0x9844
1659 #define R_AX_SEC_ERR_IMR_ISR 0x991C
1661 #define R_AX_PKTIN_SETTING 0x9A00
1664 #define R_AX_PKTIN_ERR_IMR 0x9A20
1665 #define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0)
1667 #define R_AX_PKTIN_ERR_ISR 0x9A24
1669 #define R_AX_MPDU_TX_ERR_ISR 0x9BF0
1670 #define R_AX_MPDU_TX_ERR_IMR 0x9BF4
1688 #define R_AX_MPDU_PROC 0x9C00
1690 #define B_AX_APPEND_FCS BIT(0)
1692 #define R_AX_ACTION_FWD0 0x9C04
1693 #define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
1695 #define R_AX_ACTION_FWD1 0x9C08
1697 #define R_AX_TF_FWD 0x9C14
1698 #define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
1700 #define R_AX_HW_RPT_FWD 0x9C18
1701 #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
1705 #define R_AX_CUT_AMSDU_CTRL 0x9C40
1706 #define TRXCFG_MPDU_PROC_CUT_CTRL	0x010E05F0
1708 #define R_AX_WOW_CTRL 0x9C50
1711 #define R_AX_MPDU_RX_ERR_ISR 0x9CF0
1712 #define R_AX_MPDU_RX_ERR_IMR 0x9CF4
1715 #define B_AX_GETPKTID_ERR_INT_EN BIT(0)
1718 #define R_AX_SEC_ENG_CTRL 0x9D00
1729 #define B_AX_SEC_TX_ENC BIT(0)
1731 #define R_AX_SEC_MPDU_PROC 0x9D04
1733 #define B_AX_APPEND_MIC BIT(0)
1735 #define R_AX_SEC_CAM_ACCESS 0x9D10
1736 #define R_AX_SEC_CAM_RDATA 0x9D14
1737 #define R_AX_SEC_CAM_WDATA 0x9D18
1739 #define R_AX_SEC_DEBUG 0x9D1C
1742 #define R_AX_SEC_DEBUG1 0x9D1C
1744 #define AX_TX_TO_VAL  0x2
1746 #define R_AX_SEC_TX_DEBUG 0x9D20
1747 #define R_AX_SEC_RX_DEBUG 0x9D24
1748 #define R_AX_SEC_TRX_PKT_CNT 0x9D28
1750 #define R_AX_SEC_DEBUG2 0x9D28
1752 #define B_AX_DBG_READ_MSK 0x3fffffff
1754 #define R_AX_SEC_TRX_BLK_CNT 0x9D2C
1756 #define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C
1758 #define B_AX_TX_HANG_IMR BIT(0)
1760 #define R_AX_SEC_ERROR_FLAG 0x9D30
1762 #define B_AX_TX_HANG_ERROR_V1 BIT(0)
1764 #define R_AX_SS_CTRL 0x9E10
1768 #define B_AX_SS_EN BIT(0)
1770 #define R_AX_SS2FINFO_PATH 0x9E50
1775 #define SS2F_PATH_WLCPU 0x0A
1776 #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
1778 #define R_AX_SS_MACID_PAUSE_0 0x9EB0
1779 #define B_AX_SS_MACID31_0_PAUSE_SH 0
1780 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1782 #define R_AX_SS_MACID_PAUSE_1 0x9EB4
1783 #define B_AX_SS_MACID63_32_PAUSE_SH 0
1784 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1786 #define R_AX_SS_MACID_PAUSE_2 0x9EB8
1787 #define B_AX_SS_MACID95_64_PAUSE_SH 0
1788 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1790 #define R_AX_SS_MACID_PAUSE_3 0x9EBC
1791 #define B_AX_SS_MACID127_96_PAUSE_SH 0
1792 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1794 #define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0
1797 #define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0)
1802 #define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4
1804 #define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C
1816 #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0)
1836 #define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C
1842 #define R_AX_DBG_FUN_INTF_CTL 0x9F30
1845 #define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
1846 #define R_AX_DBG_FUN_INTF_DATA 0x9F34
1847 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1849 #define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48
1855 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1857 #define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
1860 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1862 #define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
1874 #define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0)
1898 #define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C
1918 #define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0)
1920 #define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88
1925 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1927 #define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
1929 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1931 #define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
1943 #define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0)
1967 #define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC
1987 #define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0)
1989 #define R_AX_AFE_CTRL1 0x0024
1995 #define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0)
1997 #define R_AX_SYS_ISO_CTRL_EXTEND 0x0080
2003 #define R_AX_CMAC_REG_START 0xC000
2005 #define R_AX_CMAC_FUNC_EN 0xC000
2006 #define R_AX_CMAC_FUNC_EN_C1 0xE000
2017 #define B_AX_RMAC_EN BIT(0)
2019 #define R_AX_CK_EN 0xC004
2020 #define R_AX_CK_EN_C1 0xE004
2021 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
2028 #define B_AX_RMAC_CKEN BIT(0)
2030 #define R_AX_WMAC_RFMOD 0xC010
2031 #define R_AX_WMAC_RFMOD_C1 0xE010
2032 #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
2033 #define AX_WMAC_RFMOD_20M 0
2038 #define R_AX_GID_POSITION0 0xC070
2039 #define R_AX_GID_POSITION0_C1 0xE070
2040 #define R_AX_GID_POSITION1 0xC074
2041 #define R_AX_GID_POSITION1_C1 0xE074
2042 #define R_AX_GID_POSITION2 0xC078
2043 #define R_AX_GID_POSITION2_C1 0xE078
2044 #define R_AX_GID_POSITION3 0xC07C
2045 #define R_AX_GID_POSITION3_C1 0xE07C
2046 #define R_AX_GID_POSITION_EN0 0xC080
2047 #define R_AX_GID_POSITION_EN0_C1 0xE080
2048 #define R_AX_GID_POSITION_EN1 0xC084
2049 #define R_AX_GID_POSITION_EN1_C1 0xE084
2051 #define R_AX_TX_SUB_CARRIER_VALUE 0xC088
2052 #define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088
2055 #define B_AX_TXSC_20M_MASK GENMASK(3, 0)
2057 #define R_AX_PTCL_RRSR1 0xC090
2058 #define R_AX_PTCL_RRSR1_C1 0xE090
2062 #define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
2064 #define R_AX_CMAC_ERR_IMR 0xC160
2065 #define R_AX_CMAC_ERR_IMR_C1 0xE160
2072 #define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0)
2073 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
2074 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
2075 #define CMAC0_ERR_IMR_DIS 0
2076 #define CMAC1_ERR_IMR_DIS 0
2078 #define R_AX_CMAC_ERR_ISR 0xC164
2079 #define R_AX_CMAC_ERR_ISR_C1 0xE164
2086 #define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
2088 #define R_AX_PORT0_TSF_SYNC 0xC2A0
2089 #define R_AX_PORT0_TSF_SYNC_C1 0xE2A0
2090 #define R_AX_PORT1_TSF_SYNC 0xC2A4
2091 #define R_AX_PORT1_TSF_SYNC_C1 0xE2A4
2092 #define R_AX_PORT2_TSF_SYNC 0xC2A8
2093 #define R_AX_PORT2_TSF_SYNC_C1 0xE2A8
2094 #define R_AX_PORT3_TSF_SYNC 0xC2AC
2095 #define R_AX_PORT3_TSF_SYNC_C1 0xE2AC
2096 #define R_AX_PORT4_TSF_SYNC 0xC2B0
2097 #define R_AX_PORT4_TSF_SYNC_C1 0xE2B0
2103 #define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0)
2105 #define R_AX_MACID_SLEEP_0 0xC2C0
2106 #define R_AX_MACID_SLEEP_0_C1 0xE2C0
2107 #define B_AX_MACID31_0_SLEEP_SH 0
2108 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
2110 #define R_AX_MACID_SLEEP_1 0xC2C4
2111 #define R_AX_MACID_SLEEP_1_C1 0xE2C4
2112 #define B_AX_MACID63_32_SLEEP_SH 0
2113 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
2115 #define R_AX_MACID_SLEEP_2 0xC2C8
2116 #define R_AX_MACID_SLEEP_2_C1 0xE2C8
2117 #define B_AX_MACID95_64_SLEEP_SH 0
2118 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
2120 #define R_AX_MACID_SLEEP_3 0xC2CC
2121 #define R_AX_MACID_SLEEP_3_C1 0xE2CC
2122 #define B_AX_MACID127_96_SLEEP_SH 0
2123 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
2125 #define SCH_PREBKF_24US 0x18
2126 #define R_AX_PREBKF_CFG_0 0xC338
2127 #define R_AX_PREBKF_CFG_0_C1 0xE338
2128 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
2130 #define R_AX_PREBKF_CFG_1 0xC33C
2131 #define R_AX_PREBKF_CFG_1_C1 0xE33C
2135 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
2136 #define SIFS_MACTXEN_T1 0x47
2137 #define SIFS_MACTXEN_T1_V1 0x41
2139 #define R_AX_CCA_CFG_0 0xC340
2140 #define R_AX_CCA_CFG_0_C1 0xE340
2147 #define B_AX_CCA_EN BIT(0)
2149 #define R_AX_CTN_TXEN 0xC348
2150 #define R_AX_CTN_TXEN_C1 0xE348
2166 #define B_AX_CTN_TXEN_BE_0 BIT(0)
2167 #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
2169 #define R_AX_MUEDCA_BE_PARAM_0 0xC350
2170 #define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350
2173 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
2175 #define R_AX_MUEDCA_BK_PARAM_0 0xC354
2176 #define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354
2177 #define R_AX_MUEDCA_VI_PARAM_0 0xC358
2178 #define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358
2179 #define R_AX_MUEDCA_VO_PARAM_0 0xC35C
2180 #define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C
2182 #define R_AX_MUEDCA_EN 0xC370
2183 #define R_AX_MUEDCA_EN_C1 0xE370
2186 #define B_AX_MUEDCA_EN_0 BIT(0)
2188 #define R_AX_CCA_CONTROL 0xC390
2189 #define R_AX_CCA_CONTROL_C1 0xE390
2212 #define B_AX_CTN_CHK_CCA_P20 BIT(0)
2214 #define R_AX_CTN_DRV_TXEN 0xC398
2215 #define R_AX_CTN_DRV_TXEN_C1 0xE398
2218 #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
2220 #define R_AX_SCHEDULE_ERR_IMR 0xC3E8
2221 #define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8
2224 #define R_AX_SCHEDULE_ERR_ISR 0xC3EC
2225 #define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC
2227 #define R_AX_SCH_DBG_SEL 0xC3F4
2228 #define R_AX_SCH_DBG_SEL_C1 0xE3F4
2231 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
2233 #define R_AX_SCH_DBG 0xC3F8
2234 #define R_AX_SCH_DBG_C1 0xE3F8
2235 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2237 #define R_AX_SCH_EXT_CTRL 0xC3FC
2238 #define R_AX_SCH_EXT_CTRL_C1 0xE3FC
2241 #define R_AX_PORT_CFG_P0 0xC400
2242 #define R_AX_PORT_CFG_P1 0xC440
2243 #define R_AX_PORT_CFG_P2 0xC480
2244 #define R_AX_PORT_CFG_P3 0xC4C0
2245 #define R_AX_PORT_CFG_P4 0xC500
2261 #define B_AX_RXBCN_RPT_EN BIT(0)
2263 #define R_AX_TBTT_PROHIB_P0 0xC404
2264 #define R_AX_TBTT_PROHIB_P1 0xC444
2265 #define R_AX_TBTT_PROHIB_P2 0xC484
2266 #define R_AX_TBTT_PROHIB_P3 0xC4C4
2267 #define R_AX_TBTT_PROHIB_P4 0xC504
2269 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2271 #define R_AX_BCN_AREA_P0 0xC408
2272 #define R_AX_BCN_AREA_P1 0xC448
2273 #define R_AX_BCN_AREA_P2 0xC488
2274 #define R_AX_BCN_AREA_P3 0xC4C8
2275 #define R_AX_BCN_AREA_P4 0xC508
2277 #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
2279 #define R_AX_BCNERLYINT_CFG_P0 0xC40C
2280 #define R_AX_BCNERLYINT_CFG_P1 0xC44C
2281 #define R_AX_BCNERLYINT_CFG_P2 0xC48C
2282 #define R_AX_BCNERLYINT_CFG_P3 0xC4CC
2283 #define R_AX_BCNERLYINT_CFG_P4 0xC50C
2284 #define B_AX_BCNERLY_MASK GENMASK(11, 0)
2286 #define R_AX_TBTTERLYINT_CFG_P0 0xC40E
2287 #define R_AX_TBTTERLYINT_CFG_P1 0xC44E
2288 #define R_AX_TBTTERLYINT_CFG_P2 0xC48E
2289 #define R_AX_TBTTERLYINT_CFG_P3 0xC4CE
2290 #define R_AX_TBTTERLYINT_CFG_P4 0xC50E
2291 #define B_AX_TBTTERLY_MASK GENMASK(11, 0)
2293 #define R_AX_TBTT_AGG_P0 0xC412
2294 #define R_AX_TBTT_AGG_P1 0xC452
2295 #define R_AX_TBTT_AGG_P2 0xC492
2296 #define R_AX_TBTT_AGG_P3 0xC4D2
2297 #define R_AX_TBTT_AGG_P4 0xC512
2300 #define R_AX_BCN_SPACE_CFG_P0 0xC414
2301 #define R_AX_BCN_SPACE_CFG_P1 0xC454
2302 #define R_AX_BCN_SPACE_CFG_P2 0xC494
2303 #define R_AX_BCN_SPACE_CFG_P3 0xC4D4
2304 #define R_AX_BCN_SPACE_CFG_P4 0xC514
2306 #define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
2308 #define R_AX_BCN_FORCETX_P0 0xC418
2309 #define R_AX_BCN_FORCETX_P1 0xC458
2310 #define R_AX_BCN_FORCETX_P2 0xC498
2311 #define R_AX_BCN_FORCETX_P3 0xC4D8
2312 #define R_AX_BCN_FORCETX_P4 0xC518
2314 #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
2315 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2317 #define R_AX_BCN_ERR_CNT_P0 0xC420
2318 #define R_AX_BCN_ERR_CNT_P1 0xC460
2319 #define R_AX_BCN_ERR_CNT_P2 0xC4A0
2320 #define R_AX_BCN_ERR_CNT_P3 0xC4E0
2321 #define R_AX_BCN_ERR_CNT_P4 0xC520
2324 #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
2325 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2327 #define R_AX_BCN_ERR_FLAG_P0 0xC424
2328 #define R_AX_BCN_ERR_FLAG_P1 0xC464
2329 #define R_AX_BCN_ERR_FLAG_P2 0xC4A4
2330 #define R_AX_BCN_ERR_FLAG_P3 0xC4E4
2331 #define R_AX_BCN_ERR_FLAG_P4 0xC524
2338 #define B_AX_BCN_ERR_FLAG_LOCK BIT(0)
2340 #define R_AX_DTIM_CTRL_P0 0xC426
2341 #define R_AX_DTIM_CTRL_P1 0xC466
2342 #define R_AX_DTIM_CTRL_P2 0xC4A6
2343 #define R_AX_DTIM_CTRL_P3 0xC4E6
2344 #define R_AX_DTIM_CTRL_P4 0xC526
2346 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2348 #define R_AX_TBTT_SHIFT_P0 0xC428
2349 #define R_AX_TBTT_SHIFT_P1 0xC468
2350 #define R_AX_TBTT_SHIFT_P2 0xC4A8
2351 #define R_AX_TBTT_SHIFT_P3 0xC4E8
2352 #define R_AX_TBTT_SHIFT_P4 0xC528
2353 #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
2355 #define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0)
2357 #define R_AX_BCN_CNT_TMR_P0 0xC434
2358 #define R_AX_BCN_CNT_TMR_P1 0xC474
2359 #define R_AX_BCN_CNT_TMR_P2 0xC4B4
2360 #define R_AX_BCN_CNT_TMR_P3 0xC4F4
2361 #define R_AX_BCN_CNT_TMR_P4 0xC534
2362 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2364 #define R_AX_TSFTR_LOW_P0 0xC438
2365 #define R_AX_TSFTR_LOW_P1 0xC478
2366 #define R_AX_TSFTR_LOW_P2 0xC4B8
2367 #define R_AX_TSFTR_LOW_P3 0xC4F8
2368 #define R_AX_TSFTR_LOW_P4 0xC538
2369 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2371 #define R_AX_TSFTR_HIGH_P0 0xC43C
2372 #define R_AX_TSFTR_HIGH_P1 0xC47C
2373 #define R_AX_TSFTR_HIGH_P2 0xC4BC
2374 #define R_AX_TSFTR_HIGH_P3 0xC4FC
2375 #define R_AX_TSFTR_HIGH_P4 0xC53C
2376 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2378 #define R_AX_MBSSID_CTRL 0xC568
2379 #define R_AX_MBSSID_CTRL_C1 0xE568
2398 #define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590
2399 #define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590
2400 #define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
2401 #define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
2403 #define R_AX_PTCL_COMMON_SETTING_0 0xC600
2404 #define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600
2413 #define B_AX_CMAC_TX_MODE_0 BIT(0)
2415 #define R_AX_AMPDU_AGG_LIMIT 0xC610
2419 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2421 #define R_AX_AGG_LEN_HT_0 0xC614
2422 #define R_AX_AGG_LEN_HT_0_C1 0xE614
2425 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2428 #define R_AX_SIFS_SETTING 0xC624
2429 #define R_AX_SIFS_SETTING_C1 0xE624
2435 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2438 #define R_AX_TXRATE_CHK 0xC628
2439 #define R_AX_TXRATE_CHK_C1 0xE628
2444 #define B_AX_CHECK_CCK_EN BIT(0)
2446 #define R_AX_TXCNT 0xC62C
2447 #define R_AX_TXCNT_C1 0xE62C
2452 #define R_AX_MBSSID_DROP_0 0xC63C
2453 #define R_AX_MBSSID_DROP_0_C1 0xE63C
2457 #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
2459 #define R_AX_PTCLRPT_FULL_HDL 0xC660
2460 #define R_AX_PTCLRPT_FULL_HDL_C1 0xE660
2469 #define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0)
2471 #define R_AX_BT_PLT 0xC67C
2472 #define R_AX_BT_PLT_C1 0xE67C
2483 #define B_AX_TX_PLT_GNT_WL BIT(0)
2485 #define R_AX_PTCL_BSS_COLOR_0 0xC6A0
2486 #define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0
2490 #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
2492 #define R_AX_PTCL_BSS_COLOR_1 0xC6A4
2493 #define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4
2494 #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
2496 #define R_AX_PTCL_IMR0 0xC6C0
2497 #define R_AX_PTCL_IMR0_C1 0xE6C0
2515 #define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
2516 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2542 #define R_AX_PTCL_ISR0 0xC6C4
2543 #define R_AX_PTCL_ISR0_C1 0xE6C4
2545 #define S_AX_PTCL_TO_2MS 0x3F
2546 #define R_AX_PTCL_FSM_MON 0xC6E8
2547 #define R_AX_PTCL_FSM_MON_C1 0xE6E8
2549 #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
2551 #define R_AX_PTCL_TX_CTN_SEL 0xC6EC
2552 #define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC
2555 #define R_AX_PTCL_DBG_INFO 0xC6F0
2556 #define R_AX_PTCL_DBG_INFO_C1 0xE6F0
2557 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2558 #define R_AX_PTCL_DBG 0xC6F4
2559 #define R_AX_PTCL_DBG_C1 0xE6F4
2561 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2563 #define R_AX_DLE_CTRL 0xC800
2564 #define R_AX_DLE_CTRL_C1 0xE800
2574 #define R_AX_RX_ERR_FLAG 0xC800
2575 #define R_AX_RX_ERR_FLAG_C1 0xE800
2607 #define B_AX_RX_CSI_PKT_NUM_ERR BIT(0)
2609 #define R_AX_RXDMA_CTRL_0 0xC804
2610 #define R_AX_RXDMA_CTRL_0_C1 0xE804
2626 #define B_AX_RU0_PTR_FULL_MODE BIT(0)
2631 #define R_AX_RX_CTRL0 0xC808
2632 #define R_AX_RX_CTRL0_C1 0xE808
2646 #define B_AX_ORDER_FIFO_MASK GENMASK(1, 0)
2648 #define R_AX_RX_CTRL1 0xC80C
2649 #define R_AX_RX_CTRL1_C1 0xE80C
2660 #define B_AX_DBG_SEL_MASK GENMASK(1, 0)
2662 #define R_AX_RX_CTRL2 0xC810
2663 #define R_AX_RX_CTRL2_C1 0xE810
2672 #define B_AX_TXRPT_CS_MASK GENMASK(4, 0)
2674 #define R_AX_RXDMA_PKT_INFO_0 0xC814
2675 #define R_AX_RXDMA_PKT_INFO_1 0xC818
2676 #define R_AX_RXDMA_PKT_INFO_2 0xC81C
2678 #define R_AX_RX_ERR_FLAG_IMR 0xC804
2679 #define R_AX_RX_ERR_FLAG_IMR_C1 0xE804
2710 #define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0)
2762 #define R_AX_TX_ERR_FLAG_IMR 0xC870
2763 #define R_AX_TX_ERR_FLAG_IMR_C1 0xE870
2803 #define R_AX_TCR0 0xCA00
2804 #define R_AX_TCR0_C1 0xEA00
2808 #define TCR_UDF_THSD 0x6
2819 #define B_AX_TCR_DISGCLK BIT(0)
2821 #define R_AX_TCR1 0xCA04
2822 #define R_AX_TCR1_C1 0xEA04
2832 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2834 #define R_AX_MD_TSFT_STMP_CTL 0xCA08
2835 #define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08
2839 #define B_AX_UPD_TIMIE BIT(0)
2841 #define R_AX_PPWRBIT_SETTING 0xCA0C
2842 #define R_AX_PPWRBIT_SETTING_C1 0xEA0C
2844 #define R_AX_TXD_FIFO_CTRL 0xCA1C
2845 #define R_AX_TXD_FIFO_CTRL_C1 0xEA1C
2849 #define TXDFIFO_HIGH_MCS_THRE 0x7
2851 #define TXDFIFO_LOW_MCS_THRE  0x7
2853 #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
2855 #define R_AX_MACTX_DBG_SEL_CNT 0xCA20
2856 #define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20
2863 #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
2865 #define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4
2866 #define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4
2867 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2869 #define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8
2870 #define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8
2871 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2873 #define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC
2874 #define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC
2875 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2877 #define R_AX_RSP_CHK_SIG 0xCC00
2878 #define R_AX_RSP_CHK_SIG_C1 0xEC00
2888 #define B_AX_ACKTO_MASK GENMASK(7, 0)
2890 #define R_AX_TRXPTCL_RESP_0 0xCC04
2891 #define R_AX_TRXPTCL_RESP_0_C1 0xEC04
2906 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
2907 #define WMAC_SPEC_SIFS_OFDM_52A 0x15
2908 #define WMAC_SPEC_SIFS_OFDM_52B 0x11
2909 #define WMAC_SPEC_SIFS_OFDM_52C 0x11
2910 #define WMAC_SPEC_SIFS_CCK	 0xA
2912 #define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08
2913 #define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08
2924 #define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
2926 #define R_AX_MAC_LOOPBACK 0xCC20
2927 #define R_AX_MAC_LOOPBACK_C1 0xEC20
2928 #define B_AX_MACLBK_EN BIT(0)
2930 #define R_AX_WMAC_NAV_CTL 0xCC80
2931 #define R_AX_WMAC_NAV_CTL_C1 0xEC80
2937 #define NAV_12MS 0xBC
2938 #define NAV_25MS 0xC4
2939 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
2941 #define R_AX_RXTRIG_TEST_USER_2 0xCCB0
2942 #define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0
2948 #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
2950 #define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC
2951 #define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC
2962 #define B_AX_TMAC_MACTX BIT(0)
2981 #define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0
2982 #define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0
2991 #define B_AX_MACTX_ERROR_FLAG_CLR BIT(0)
2993 #define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
2994 #define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
2995 #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
2997 #define R_AX_WMAC_TX_TF_INFO_1 0xCCD4
2998 #define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4
2999 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
3001 #define R_AX_WMAC_TX_TF_INFO_2 0xCCD8
3002 #define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8
3003 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
3005 #define R_AX_TMAC_ERR_IMR_ISR 0xCCEC
3006 #define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC
3020 #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
3030 #define R_AX_DBGSEL_TRXPTCL 0xCCF4
3031 #define R_AX_DBGSEL_TRXPTCL_C1 0xECF4
3032 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
3034 #define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8
3035 #define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8
3042 #define B_AX_PHY_TXON_TIMEOUT_EN BIT(0)
3056 #define R_AX_PHYINFO_ERR_IMR 0xCCFC
3057 #define R_AX_PHYINFO_ERR_IMR_C1 0xECFC
3070 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
3078 #define R_AX_PHYINFO_ERR_ISR 0xCCFC
3079 #define R_AX_PHYINFO_ERR_ISR_C1 0xECFC
3081 #define R_AX_BFMER_CTRL_0 0xCD78
3082 #define R_AX_BFMER_CTRL_0_C1 0xED78
3087 #define B_AX_BFMER_VHT_BFPRT_CHK BIT(0)
3089 #define R_AX_BFMEE_RESP_OPTION 0xCD80
3090 #define R_AX_BFMEE_RESP_OPTION_C1 0xED80
3093 #define BFRP_RX_STANDBY_TIMER_KEEP 0x0
3094 #define BFRP_RX_STANDBY_TIMER_RELEASE 0x1
3097 #define BFRP_RX_STANDBY_TIMER		0x0
3098 #define NDP_RX_STANDBY_TIMER		0xFF
3101 #define B_AX_BFMEE_HT_NDPA_EN BIT(0)
3103 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88
3104 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88
3105 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94
3106 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94
3125 #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
3127 #define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C
3128 #define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C
3129 #define CSI_RRSC_BMAP 0x29292911
3131 #define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90
3132 #define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90
3135 #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
3136 #define CSI_INIT_RATE_HE		0x3
3137 #define CSI_INIT_RATE_VHT		0x3
3138 #define CSI_INIT_RATE_HT		0x3
3140 #define R_AX_RCR 0xCE00
3141 #define R_AX_RCR_C1 0xEE00
3144 #define B_AX_CH_EN_MASK GENMASK(3, 0)
3146 #define R_AX_DLK_PROTECT_CTL 0xCE02
3147 #define R_AX_DLK_PROTECT_CTL_C1 0xEE02
3151 #define R_AX_PLCP_HDR_FLTR 0xCE04
3152 #define R_AX_PLCP_HDR_FLTR_C1 0xEE04
3160 #define B_AX_CCK_CRC_CHK BIT(0)
3162 #define R_AX_RX_FLTR_OPT 0xCE20
3163 #define R_AX_RX_FLTR_OPT_C1 0xEE20
3168 #define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f
3182 #define B_AX_SNIFFER_MODE BIT(0)
3190 #define R_AX_CTRL_FLTR 0xCE24
3191 #define R_AX_CTRL_FLTR_C1 0xEE24
3192 #define R_AX_MGNT_FLTR 0xCE28
3193 #define R_AX_MGNT_FLTR_C1 0xEE28
3194 #define R_AX_DATA_FLTR 0xCE2C
3195 #define R_AX_DATA_FLTR_C1 0xEE2C
3196 #define RX_FLTR_FRAME_DROP	0x00000000
3197 #define RX_FLTR_FRAME_TO_HOST	0x55555555
3198 #define RX_FLTR_FRAME_TO_WLCPU	0xAAAAAAAA
3200 #define R_AX_ADDR_CAM_CTRL 0xCE34
3201 #define R_AX_ADDR_CAM_CTRL_C1 0xEE34
3207 #define B_AX_ADDR_CAM_EN BIT(0)
3209 #define R_AX_RESPBA_CAM_CTRL 0xCE3C
3210 #define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C
3212 #define B_AX_BACAM_RST_MASK GENMASK(1, 0)
3215 #define R_AX_PPDU_STAT 0xCE40
3216 #define R_AX_PPDU_STAT_C1 0xEE40
3223 #define B_AX_PPDU_STAT_RPT_EN BIT(0)
3225 #define R_AX_RX_SR_CTRL 0xCE4A
3226 #define R_AX_RX_SR_CTRL_C1 0xEE4A
3227 #define B_AX_SR_EN BIT(0)
3229 #define R_AX_CSIRPT_OPTION 0xCE64
3230 #define R_AX_CSIRPT_OPTION_C1 0xEE64
3234 #define R_AX_RX_STATE_MONITOR 0xCEF0
3235 #define R_AX_RX_STATE_MONITOR_C1 0xEEF0
3236 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
3240 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
3242 #define R_AX_RMAC_ERR_ISR 0xCEF4
3243 #define R_AX_RMAC_ERR_ISR_C1 0xEEF4
3260 #define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0)
3274 #define R_AX_RX_ERR_IMR 0xCEF8
3275 #define R_AX_RX_ERR_IMR_C1 0xEEF8
3285 #define B_AX_RX_ERR_CCA_TO_MSK BIT(0)
3307 #define R_AX_RMAC_PLCP_MON 0xCEF8
3308 #define R_AX_RMAC_PLCP_MON_C1 0xEEF8
3309 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
3311 #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
3313 #define R_AX_RX_DEBUG_SELECT 0xCEFC
3314 #define R_AX_RX_DEBUG_SELECT_C1 0xEEFC
3315 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
3317 #define R_AX_PWR_RATE_CTRL 0xD200
3318 #define R_AX_PWR_RATE_CTRL_C1 0xF200
3321 #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
3323 #define R_AX_PWR_RATE_OFST_CTRL 0xD204
3324 #define R_AX_PWR_COEXT_CTRL 0xD220
3328 #define R_AX_PWR_SWING_OTHER_CTRL0 0xD230
3329 #define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230
3330 #define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0)
3332 #define R_AX_PWR_UL_CTRL0 0xD240
3333 #define R_AX_PWR_UL_CTRL2 0xD248
3334 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
3335 #define B_AX_PWR_UL_CTRL2_MASK 0x07700007
3337 #define R_AX_PWR_NORM_FORCE1 0xD260
3338 #define R_AX_PWR_NORM_FORCE1_C1 0xF260
3356 #define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0)
3358 #define R_AX_PWR_UL_TB_CTRL 0xD288
3360 #define R_AX_PWR_UL_TB_1T 0xD28C
3361 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3362 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
3363 #define R_AX_PWR_UL_TB_2T 0xD290
3364 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3365 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3366 #define R_AX_PWR_BY_RATE_TABLE0 0xD2C0
3367 #define R_AX_PWR_BY_RATE_TABLE6 0xD2D8
3368 #define R_AX_PWR_BY_RATE_TABLE10 0xD2E8
3372 #define R_AX_PWR_LMT_TABLE0 0xD2EC
3373 #define R_AX_PWR_LMT_TABLE9 0xD310
3374 #define R_AX_PWR_LMT_TABLE19 0xD338
3378 #define R_AX_PWR_RU_LMT_TABLE0 0xD33C
3379 #define R_AX_PWR_RU_LMT_TABLE5 0xD350
3380 #define R_AX_PWR_RU_LMT_TABLE11 0xD368
3384 #define R_AX_PWR_MACID_LMT_TABLE0 0xD36C
3385 #define R_AX_PWR_MACID_LMT_TABLE127 0xD568
3387 #define R_AX_PATH_COM0 0xD800
3388 #define AX_PATH_COM0_DFVAL 0x00000000
3389 #define AX_PATH_COM0_PATHA 0x08889880
3390 #define AX_PATH_COM0_PATHB 0x11111900
3391 #define AX_PATH_COM0_PATHAB 0x19999980
3392 #define R_AX_PATH_COM1 0xD804
3393 #define AX_PATH_COM1_DFVAL 0x00000000
3394 #define AX_PATH_COM1_PATHA 0x13111111
3395 #define AX_PATH_COM1_PATHB 0x23222222
3396 #define AX_PATH_COM1_PATHAB 0x33333333
3397 #define R_AX_PATH_COM2 0xD808
3398 #define AX_PATH_COM2_DFVAL 0x00000000
3399 #define AX_PATH_COM2_PATHA 0x01209313
3400 #define AX_PATH_COM2_PATHB 0x01209323
3401 #define AX_PATH_COM2_PATHAB 0x01209333
3402 #define R_AX_PATH_COM3 0xD80C
3403 #define AX_PATH_COM3_DFVAL 0x49249249
3404 #define R_AX_PATH_COM4 0xD810
3405 #define AX_PATH_COM4_DFVAL 0x1C9C9C49
3406 #define R_AX_PATH_COM5 0xD814
3407 #define AX_PATH_COM5_DFVAL 0x39393939
3408 #define R_AX_PATH_COM6 0xD818
3409 #define AX_PATH_COM6_DFVAL 0x39393939
3410 #define R_AX_PATH_COM7 0xD81C
3411 #define AX_PATH_COM7_DFVAL 0x39393939
3412 #define AX_PATH_COM7_PATHA 0x39393939
3413 #define AX_PATH_COM7_PATHB 0x39383939
3414 #define AX_PATH_COM7_PATHAB 0x39393939
3415 #define R_AX_PATH_COM8 0xD820
3416 #define AX_PATH_COM8_DFVAL 0x00000000
3417 #define AX_PATH_COM8_PATHA 0x00003939
3418 #define AX_PATH_COM8_PATHB 0x00003938
3419 #define AX_PATH_COM8_PATHAB 0x00003939
3420 #define R_AX_PATH_COM9 0xD824
3421 #define AX_PATH_COM9_DFVAL 0x000007C0
3422 #define R_AX_PATH_COM10 0xD828
3423 #define AX_PATH_COM10_DFVAL 0xE0000000
3424 #define R_AX_PATH_COM11 0xD82C
3425 #define AX_PATH_COM11_DFVAL 0x00000000
3426 #define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848
3428 #define R_AX_TSSI_CTRL_HEAD 0xD908
3429 #define R_AX_BANDEDGE_CFG 0xD94C
3431 #define R_AX_TSSI_CTRL_TAIL 0xD95C
3433 #define R_AX_TXPWR_IMR 0xD9E0
3434 #define R_AX_TXPWR_IMR_C1 0xF9E0
3435 #define R_AX_TXPWR_ISR 0xD9E4
3436 #define R_AX_TXPWR_ISR_C1 0xF9E4
3438 #define R_AX_BTC_CFG 0xDA00
3453 #define B_AX_WL_SRC BIT(0)
3455 #define R_AX_RTK_MODE_CFG_V1 0xDA04
3456 #define R_AX_RTK_MODE_CFG_V1_C1 0xFA04
3463 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3465 #define R_AX_WL_PRI_MSK 0xDA10
3468 #define R_AX_BT_CNT_CFG 0xDA10
3469 #define R_AX_BT_CNT_CFG_C1 0xFA10
3471 #define B_AX_BT_CNT_EN BIT(0)
3473 #define R_BTC_BT_CNT_HIGH 0xDA14
3474 #define R_BTC_BT_CNT_LOW 0xDA18
3476 #define R_AX_BTC_FUNC_EN 0xDA20
3477 #define R_AX_BTC_FUNC_EN_C1 0xFA20
3479 #define B_AX_PTA_EDCCA_EN BIT(0)
3481 #define R_BTC_COEX_WL_REQ 0xDA24
3485 #define R_BTC_BREAK_TABLE 0xDA2C
3486 #define BTC_BREAK_PARAM 0xf0ffffff
3488 #define R_BTC_BT_COEX_MSK_TABLE 0xDA30
3492 #define R_AX_BT_COEX_CFG_2 0xDA34
3493 #define R_AX_BT_COEX_CFG_2_C1 0xFA34
3496 #define B_AX_TIMER_MASK GENMASK(7, 0)
3499 #define R_AX_CSR_MODE 0xDA40
3500 #define R_AX_CSR_MODE_C1 0xFA40
3503 #define MAC_AX_CSR_DELAY 0
3511 #define B_AX_ENHANCED_BT BIT(0)
3513 #define R_AX_BT_BREAK_TABLE 0xDA44
3515 #define R_AX_BT_STAST_HIGH 0xDA44
3517 #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
3518 #define R_AX_BT_STAST_LOW 0xDA48
3519 #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
3522 #define R_AX_GNT_SW_CTRL 0xDA48
3523 #define R_AX_GNT_SW_CTRL_C1 0xFA48
3545 #define B_AX_GNT_WL_BB_SWCTRL BIT(0)
3547 #define R_AX_GNT_VAL 0x0054
3553 #define R_AX_GNT_VAL_V1 0xDA4C
3559 #define R_AX_TDMA_MODE 0xDA4C
3560 #define R_AX_TDMA_MODE_C1 0xFA4C
3569 #define B_AX_RTK_BT_ENABLE BIT(0)
3571 #define R_AX_BT_COEX_CFG_5 0xDA6C
3572 #define R_AX_BT_COEX_CFG_5_C1 0xFA6C
3574 #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
3577 #define R_AX_LTE_CTRL 0xDAF0
3578 #define R_AX_LTE_WDATA 0xDAF4
3579 #define R_AX_LTE_RDATA 0xDAF8
3581 #define R_AX_MACID_ANT_TABLE 0xDC00
3582 #define R_AX_MACID_ANT_TABLE_LAST 0xDDFC
3584 #define CMAC1_START_ADDR 0xE000
3585 #define CMAC1_END_ADDR 0xFFFF
3586 #define R_AX_CMAC_REG_END 0xFFFF
3588 #define R_AX_LTE_SW_CFG_1 0x0038
3589 #define R_AX_LTE_SW_CFG_1_C1 0x2038
3614 #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
3616 #define R_AX_LTE_SW_CFG_2 0x003C
3617 #define R_AX_LTE_SW_CFG_2_C1 0x203C
3626 #define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
3628 #define R_BE_FILTER_MODEL_ADDR 0x0C04
3630 #define R_BE_RX_FLTR_OPT 0x11420
3631 #define R_BE_RX_FLTR_OPT_C1 0x15420
3647 #define B_BE_SNIFFER_MODE BIT(0)
3649 #define RR_MOD 0x00
3650 #define RR_MOD_V1 0x10000
3657 #define RR_MOD_V_DOWN 0x0
3658 #define RR_MOD_V_STANDBY 0x1
3659 #define RR_TXAGC 0x10001
3660 #define RR_MOD_V_TX 0x2
3661 #define RR_MOD_V_RX 0x3
3662 #define RR_MOD_V_TXIQK 0x4
3663 #define RR_MOD_V_DPK 0x5
3664 #define RR_MOD_V_RXK1 0x6
3665 #define RR_MOD_V_RXK2 0x7
3670 #define RR_MODOPT 0x01
3671 #define RR_MODOPT_M_TXPWR GENMASK(5, 0)
3672 #define RR_WLSEL 0x02
3674 #define RR_RSV1 0x05
3675 #define RR_RSV1_RST BIT(0)
3676 #define RR_BBDC 0x10005
3677 #define RR_BBDC_SEL BIT(0)
3678 #define RR_DTXLOK 0x08
3679 #define RR_RSV2 0x09
3680 #define RR_LOKVB 0x0a
3683 #define RR_TXIG 0x11
3686 #define RR_TXIG_GR0 GENMASK(1, 0)
3687 #define RR_CHTR 0x17
3689 #define RR_CHTR_TXRX GENMASK(9, 0)
3690 #define RR_CFGCH 0x18
3691 #define RR_CFGCH_V1 0x10018
3693 #define CFGCH_BAND1_2G 0
3701 #define CFGCH_BAND0_2G 0
3703 #define CFGCH_BAND0_6G 0
3705 #define RR_CFGCH_CH GENMASK(7, 0)
3709 #define CFGCH_BW_160M 0
3710 #define RR_APK 0x19
3712 #define RR_BTC 0x1a
3715 #define RR_RCKC 0x1b
3717 #define RR_RCKS 0x1c
3718 #define RR_RCKO 0x1d
3720 #define RR_RXKPLL 0x1e
3721 #define RR_RXKPLL_OFF GENMASK(5, 0)
3723 #define RR_RSV4 0x1f
3725 #define RR_RSV4_PLLCH GENMASK(9, 0)
3726 #define RR_RXK 0x20
3730 #define RR_LUTWA 0x33
3731 #define RR_LUTWA_MASK GENMASK(9, 0)
3732 #define RR_LUTWA_M1 GENMASK(7, 0)
3733 #define RR_LUTWA_M2 GENMASK(4, 0)
3734 #define RR_LUTWD1 0x3e
3735 #define RR_LUTWD0 0x3f
3737 #define RR_LUTWD0_LB GENMASK(5, 0)
3738 #define RR_TM 0x42
3741 #define RR_TM2 0x43
3743 #define RR_TXG1 0x51
3746 #define RR_TXG2 0x52
3748 #define RR_BSPAD 0x54
3749 #define RR_TXGA 0x55
3751 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
3752 #define RR_TXGA_LOK_EN BIT(0)
3753 #define RR_TXGA_V1 0x10055
3755 #define RR_GAINTX 0x56
3756 #define RR_GAINTX_ALL GENMASK(15, 0)
3758 #define RR_GAINTX_BB GENMASK(4, 0)
3759 #define RR_TXMO 0x58
3764 #define RR_TXA 0x5d
3766 #define RR_TXRSV 0x5c
3768 #define RR_BIAS 0x5e
3770 #define RR_TXAC 0x5f
3771 #define RR_TXAC_IQG GENMASK(3, 0)
3772 #define RR_BIASA 0x60
3775 #define RR_BIASA_A GENMASK(2, 0)
3776 #define RR_BIASA2 0x63
3778 #define RR_TXATANK 0x64
3781 #define RR_TXA2 0x65
3783 #define RR_TRXIQ 0x66
3784 #define RR_RSV6 0x6d
3785 #define RR_TXVBUF 0x7c
3787 #define RR_TXPOW 0x7f
3791 #define RR_RXPOW 0x80
3793 #define RR_RXBB 0x83
3798 #define RR_RXBB_FATT GENMASK(7, 0)
3800 #define RR_RXBB_ATTC GENMASK(2, 0)
3801 #define RR_RXG 0x84
3803 #define RR_XGLNA2 0x85
3804 #define RR_XGLNA2_SW GENMASK(1, 0)
3805 #define RR_RXAE 0x89
3806 #define RR_RXAE_IQKMOD GENMASK(3, 0)
3807 #define RR_RXA 0x8a
3809 #define RR_RXA_LNA 0x8b
3810 #define RR_RXA2 0x8c
3817 #define RR_RXA2_HATT GENMASK(6, 0)
3818 #define RR_RXA2_ATT GENMASK(3, 0)
3819 #define RR_RXIQGEN 0x8d
3822 #define RR_RXBB2 0x8f
3828 #define RR_XALNA2 0x90
3830 #define RR_XALNA2_SW GENMASK(1, 0)
3831 #define RR_DCK 0x92
3836 #define RR_DCK_LV BIT(0)
3837 #define RR_DCK1 0x93
3841 #define RR_DCK1_CLR GENMASK(3, 0)
3843 #define RR_DCK2 0x94
3845 #define RR_DCKC 0x95
3847 #define RR_IQGEN 0x97
3849 #define RR_TXIQK 0x98
3851 #define RR_TXIQK_ATT1 GENMASK(6, 0)
3852 #define RR_TIA 0x9e
3854 #define RR_MIXER 0x9f
3856 #define RR_POW 0xa0
3858 #define RR_LOGEN 0xa3
3860 #define RR_SX 0xaf
3861 #define RR_IBD 0xc9
3862 #define RR_IBD_VAL GENMASK(4, 0)
3863 #define RR_LDO 0xb1
3865 #define RR_VCO 0xb2
3867 #define RR_VCI 0xb3
3869 #define RR_LPF 0xb7
3871 #define RR_XTALX2 0xb8
3872 #define RR_MALSEL 0xbe
3873 #define RR_SYNFB 0xc5
3875 #define RR_AACK 0xca
3876 #define RR_LCKST 0xcf
3877 #define RR_LCKST_BIN BIT(0)
3878 #define RR_LCK_TRG 0xd3
3881 #define RR_MMD 0xd5
3884 #define RR_IQKPLL 0xdc
3886 #define RR_SYNLUT 0xdd
3888 #define RR_RCKD 0xde
3891 #define RR_TXADBG 0xde
3892 #define RR_LUTDBG 0xdf
3895 #define RR_LUTPLL 0xec
3897 #define RR_LUTWE2 0xee
3900 #define RR_LUTWE 0xef
3902 #define RR_RFC 0xf0
3906 #define R_UPD_P0 0x0000
3907 #define R_RSTB_WATCH_DOG 0x000C
3908 #define B_P0_RSTB_WATCH_DOG BIT(0)
3911 #define R_ANAPAR_PW15 0x030C
3915 #define R_ANAPAR 0x032C
3921 #define B_ANAPAR_14 GENMASK(15, 0)
3922 #define R_RFE_E_A2 0x0334
3923 #define R_RFE_O_SEL_A2 0x0338
3924 #define R_RFE_SEL0_A2 0x033C
3925 #define B_RFE_SEL0_MASK GENMASK(1, 0)
3926 #define R_RFE_SEL32_A2 0x0340
3927 #define R_CIRST 0x035c
3929 #define R_SWSI_DATA_V1 0x0370
3930 #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
3934 #define R_SWSI_BIT_MASK_V1 0x0374
3935 #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
3936 #define R_SWSI_READ_ADDR_V1 0x0378
3937 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
3939 #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
3940 #define R_UPD_CLK_ADC 0x0700
3944 #define R_RSTB_ASYNC 0x0704
3946 #define R_P0_ANT_SW 0x0728
3948 #define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
3949 #define R_MAC_PIN_SEL 0x0734
3951 #define R_PLCP_HISTOGRAM 0x0738
3957 #define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C
3958 #define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f
3959 #define R_PHY_STS_BITMAP_R2T 0x0740
3960 #define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744
3961 #define R_PHY_STS_BITMAP_OFDM_BRK 0x0748
3962 #define R_PHY_STS_BITMAP_CCK_BRK 0x074C
3963 #define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750
3964 #define R_PHY_STS_BITMAP_HE_MU 0x0754
3965 #define R_PHY_STS_BITMAP_VHT_MU 0x0758
3966 #define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C
3967 #define R_PHY_STS_BITMAP_TRIGBASE 0x0760
3968 #define R_PHY_STS_BITMAP_CCK 0x0764
3969 #define R_PHY_STS_BITMAP_LEGACY 0x0768
3970 #define R_PHY_STS_BITMAP_HT 0x076C
3971 #define R_PHY_STS_BITMAP_VHT 0x0770
3972 #define R_PHY_STS_BITMAP_HE 0x0774
3973 #define R_PMAC_GNT 0x0980
3974 #define B_PMAC_GNT_TXEN BIT(0)
3978 #define R_PMAC_RX_CFG1 0x0988
3979 #define B_PMAC_OPT1_MSK GENMASK(11, 0)
3980 #define R_PMAC_RXMOD 0x0994
3982 #define R_MAC_SEL 0x09A4
3987 #define R_PMAC_TX_CTRL 0x09C0
3988 #define B_PMAC_TXEN_DIS BIT(0)
3989 #define R_PMAC_TX_PRD 0x09C4
3991 #define B_PMAC_CTX_EN BIT(0)
3993 #define R_PMAC_TX_CNT 0x09C8
3994 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
3995 #define R_P80_AT_HIGH_FREQ 0x09D8
3997 #define R_DBCC_80P80_SEL_EVM_RPT 0x0A10
3998 #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0)
3999 #define R_CCX 0x0C00
4004 #define B_CCX_EN_MSK BIT(0)
4005 #define R_IFS_COUNTER 0x0C28
4010 #define R_IFS_T1 0x0C2C
4013 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
4014 #define R_IFS_T2 0x0C30
4017 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
4018 #define R_IFS_T3 0x0C34
4021 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
4022 #define R_IFS_T4 0x0C38
4025 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
4026 #define R_PD_CTRL 0x0C3C
4028 #define R_IOQ_IQK_DPK 0x0C60
4030 #define R_GNT_BT_WGT_EN 0x0C6C
4032 #define R_PD_ARBITER_OFF 0x0C80
4034 #define R_SNDCCA_A1 0x0C9C
4036 #define R_SNDCCA_A2 0x0CA0
4038 #define R_RXHT_MCS_LIMIT 0x0D18
4040 #define R_RXVHT_MCS_LIMIT 0x0D18
4042 #define R_P0_EN_SOUND_WO_NDP 0x0D7C
4044 #define R_RXHE 0x0D80
4048 #define R_SPOOF_ASYNC_RST 0x0D84
4050 #define R_NDP_BRK0 0xDA0
4051 #define R_NDP_BRK1 0xDA4
4052 #define B_NDP_RU_BRK BIT(0)
4053 #define R_BRK_ASYNC_RST_EN_1 0x0DC0
4054 #define R_BRK_ASYNC_RST_EN_2 0x0DC4
4055 #define R_BRK_ASYNC_RST_EN_3 0x0DC8
4056 #define R_S0_HW_SI_DIS 0x1200
4058 #define R_P0_RXCK 0x12A0
4066 #define R_P0_RFMODE 0x12AC
4069 #define R_P0_RFMODE_ORI_RX 0x12AC
4071 #define R_P0_RFMODE_FTM_RX 0x12B0
4072 #define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
4073 #define R_P0_NRBW 0x12B8
4075 #define R_S0_RXDC 0x12D4
4078 #define R_S0_RXDC2 0x12D8
4082 #define B_S0_RXDC2_Q2 GENMASK(3, 0)
4083 #define R_CFO_COMP_SEG0_L 0x1384
4084 #define R_CFO_COMP_SEG0_H 0x1388
4085 #define R_CFO_COMP_SEG0_CTRL 0x138C
4086 #define R_DBG32_D 0x1730
4087 #define R_SWSI_V1 0x174C
4091 #define R_TX_COUNTER 0x1A40
4092 #define R_IFS_CLM_TX_CNT 0x1ACC
4093 #define R_IFS_CLM_TX_CNT_V1 0x0ECC
4095 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
4096 #define R_IFS_CLM_CCA 0x1AD0
4097 #define R_IFS_CLM_CCA_V1 0x0ED0
4099 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
4100 #define R_IFS_CLM_FA 0x1AD4
4101 #define R_IFS_CLM_FA_V1 0x0ED4
4103 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
4104 #define R_IFS_HIS 0x1AD8
4105 #define R_IFS_HIS_V1 0x0ED8
4109 #define B_IFS_T1_HIS_MSK GENMASK(7, 0)
4110 #define R_IFS_AVG_L 0x1ADC
4111 #define R_IFS_AVG_L_V1 0x0EDC
4113 #define B_IFS_T1_AVG_MSK GENMASK(15, 0)
4114 #define R_IFS_AVG_H 0x1AE0
4115 #define R_IFS_AVG_H_V1 0x0EE0
4117 #define B_IFS_T3_AVG_MSK GENMASK(15, 0)
4118 #define R_IFS_CCA_L 0x1AE4
4119 #define R_IFS_CCA_L_V1 0x0EE4
4121 #define B_IFS_T1_CCA_MSK GENMASK(15, 0)
4122 #define R_IFS_CCA_H 0x1AE8
4123 #define R_IFS_CCA_H_V1 0x0EE8
4125 #define B_IFS_T3_CCA_MSK GENMASK(15, 0)
4126 #define R_IFSCNT 0x1AEC
4127 #define R_IFSCNT_V1 0x0EEC
4129 #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
4130 #define R_TXAGC_TP 0x1C04
4131 #define B_TXAGC_TP GENMASK(2, 0)
4132 #define R_TSSI_THER 0x1C10
4134 #define R_TSSI_CWRPT 0x1C18
4136 #define B_TSSI_CWRPT GENMASK(8, 0)
4137 #define R_TXAGC_BTP 0x1CA0
4139 #define R_TXAGC_BB 0x1C60
4142 #define B_TXAGC_RF GENMASK(5, 0)
4143 #define R_PATH0_TXPWR 0x1C78
4144 #define B_PATH0_TXPWR GENMASK(8, 0)
4145 #define R_S0_ADDCK 0x1E00
4146 #define B_S0_ADDCK_I GENMASK(9, 0)
4148 #define R_ADC_FIFO 0x20fc
4155 #define R_TXFIR0 0x2300
4156 #define B_TXFIR_C01 GENMASK(23, 0)
4157 #define R_TXFIR2 0x2304
4158 #define B_TXFIR_C23 GENMASK(23, 0)
4159 #define R_TXFIR4 0x2308
4160 #define B_TXFIR_C45 GENMASK(23, 0)
4161 #define R_TXFIR6 0x230c
4162 #define B_TXFIR_C67 GENMASK(23, 0)
4163 #define R_TXFIR8 0x2310
4164 #define B_TXFIR_C89 GENMASK(23, 0)
4165 #define R_TXFIRA 0x2314
4166 #define B_TXFIR_CAB GENMASK(23, 0)
4167 #define R_TXFIRC 0x2318
4168 #define B_TXFIR_CCD GENMASK(23, 0)
4169 #define R_TXFIRE 0x231c
4170 #define B_TXFIR_CEF GENMASK(23, 0)
4171 #define R_11B_RX_V1 0x2320
4172 #define B_11B_RXCCA_DIS_V1 BIT(0)
4173 #define R_RPL_OFST 0x2340
4175 #define R_RXCCA 0x2344
4177 #define R_RXCCA_V1 0x2320
4178 #define B_RXCCA_DIS_V1 BIT(0)
4179 #define R_RXSC 0x237C
4180 #define B_RXSC_EN BIT(0)
4181 #define R_RX_RPL_OFST 0x23AC
4182 #define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
4183 #define R_RXSCOBC 0x23B0
4184 #define B_RXSCOBC_TH GENMASK(18, 0)
4185 #define R_RXSCOCCK 0x23B4
4186 #define B_RXSCOCCK_TH GENMASK(18, 0)
4187 #define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410
4190 #define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10
4191 #define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0)
4192 #define R_P1_EN_SOUND_WO_NDP 0x2D7C
4194 #define R_S1_HW_SI_DIS 0x3200
4196 #define R_P1_RXCK 0x32A0
4201 #define R_P1_RFMODE 0x32AC
4204 #define R_P1_RFMODE_ORI_RX 0x32AC
4206 #define R_P1_RFMODE_FTM_RX 0x32B0
4207 #define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
4208 #define R_P1_DBGMOD 0x32B8
4210 #define R_S1_RXDC 0x32D4
4213 #define R_S1_RXDC2 0x32D8
4216 #define B_S1_RXDC2_Q2 GENMASK(3, 0)
4217 #define R_TXAGC_BB_S1 0x3C60
4220 #define R_PATH1_TXPWR 0x3C78
4221 #define B_PATH1_TXPWR GENMASK(8, 0)
4222 #define R_S1_ADDCK 0x3E00
4223 #define B_S1_ADDCK_I GENMASK(9, 0)
4225 #define R_MUIC 0x40F8
4226 #define B_MUIC_EN BIT(0)
4227 #define R_DCFO 0x4264
4228 #define B_DCFO GENMASK(7, 0)
4229 #define R_SEG0CSI 0x42AC
4230 #define R_SEG0CSI_V1 0x42B0
4231 #define B_SEG0CSI_IDX GENMASK(10, 0)
4232 #define R_SEG0CSI_EN 0x42C4
4233 #define R_SEG0CSI_EN_V1 0x42C8
4235 #define R_BSS_CLR_MAP 0x43ac
4236 #define R_BSS_CLR_MAP_V1 0x43B0
4240 #define R_CFO_TRK0 0x4404
4241 #define R_CFO_TRK1 0x440C
4243 #define R_T2F_GI_COMB 0x4424
4245 #define R_BT_DYN_DC_EST_EN 0x441C
4246 #define R_BT_DYN_DC_EST_EN_V1 0x4420
4248 #define R_ASSIGN_SBD_OPT_V1 0x4440
4250 #define R_ASSIGN_SBD_OPT 0x4450
4252 #define R_DCFO_COMP_S0 0x448C
4253 #define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
4254 #define R_DCFO_WEIGHT 0x4490
4256 #define R_DCFO_OPT 0x4494
4259 #define R_BANDEDGE 0x4498
4261 #define R_DPD_BF 0x44a0
4263 #define B_DPD_BF_SCA GENMASK(6, 0)
4264 #define R_TXPATH_SEL 0x458C
4266 #define R_TXPWR 0x4594
4268 #define R_TXNSS_MAP 0x45B4
4270 #define R_PCOEFF0_V1 0x45BC
4271 #define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
4272 #define R_PCOEFF2_V1 0x45CC
4273 #define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
4274 #define R_PCOEFF4_V1 0x45D0
4275 #define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
4276 #define R_PCOEFF6_V1 0x45D4
4277 #define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
4278 #define R_PCOEFF8_V1 0x45D8
4279 #define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
4280 #define R_PCOEFFA_V1 0x45C0
4281 #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
4282 #define R_PCOEFFC_V1 0x45C4
4283 #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
4284 #define R_PCOEFFE_V1 0x45C8
4285 #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
4286 #define R_PATH0_IB_PKPW 0x4628
4288 #define R_PATH0_LNA_ERR1 0x462C
4292 #define R_PATH0_LNA_ERR2 0x4630
4295 #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
4296 #define R_PATH0_LNA_ERR3 0x4634
4300 #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
4301 #define R_PATH0_LNA_ERR4 0x4638
4305 #define R_PATH0_LNA_ERR5 0x463C
4306 #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
4307 #define R_PATH0_TIA_ERR_G0 0x4640
4310 #define R_PATH0_TIA_ERR_G1 0x4644
4313 #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
4314 #define R_PATH0_IB_PBK 0x4650
4316 #define R_PATH0_RXB_INIT 0x4658
4318 #define R_PATH0_LNA_INIT 0x4668
4319 #define R_PATH0_LNA_INIT_V1 0x472C
4321 #define R_PATH0_BTG 0x466C
4323 #define R_PATH0_TIA_INIT 0x4674
4325 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0
4326 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24
4327 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8
4329 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
4330 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28
4331 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC
4333 #define R_PATH0_RXB_INIT_V1 0x46A8
4335 #define R_PATH0_G_LNA6_OP1DB_V1 0x4688
4337 #define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694
4338 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
4339 #define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694
4342 #define R_CDD_EVM_CHK_EN 0x46C0
4343 #define B_CDD_EVM_CHK_EN BIT(0)
4344 #define R_PATH0_BAND_SEL_V1 0x4738
4346 #define R_PATH0_BT_SHARE_V1 0x4738
4348 #define R_PATH0_BTG_PATH_V1 0x4738
4350 #define R_P0_NBIIDX 0x469C
4351 #define B_P0_NBIIDX_VAL GENMASK(11, 0)
4353 #define R_P0_BACKOFF_IBADC_V1 0x469C
4356 #define R_P1_MODE 0x4718
4358 #define R_P0_AGC_CTL 0x4730
4360 #define R_PATH1_LNA_INIT 0x473C
4361 #define R_PATH1_LNA_INIT_V1 0x4A80
4363 #define R_PATH0_TIA_INIT_V1 0x473C
4365 #define R_PATH1_TIA_INIT 0x4748
4367 #define R_PATH1_BTG 0x4740
4369 #define R_PATH1_RXB_INIT 0x472C
4371 #define R_PATH1_G_LNA6_OP1DB_V1 0x476C
4373 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774
4374 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8
4375 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8
4377 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
4378 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC
4379 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC
4381 #define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
4382 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
4383 #define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778
4385 #define R_PATH1_BAND_SEL_V1 0x4AA4
4387 #define R_PATH1_BT_SHARE_V1 0x4AA4
4389 #define R_PATH1_BTG_PATH_V1 0x4AA4
4391 #define R_P1_NBIIDX 0x4770
4392 #define B_P1_NBIIDX_VAL GENMASK(11, 0)
4394 #define R_PKT_CTRL 0x47D4
4396 #define R_SEG0R_PD 0x481C
4397 #define R_SEG0R_PD_V1 0x4860
4398 #define R_SEG0R_PD_V2 0x6A74
4399 #define R_SEG0R_EDCCA_LVL 0x4840
4400 #define R_SEG0R_EDCCA_LVL_V1 0x4884
4403 #define B_SEG0R_EDCCA_LVL_A_MSK GENMASK(7, 0)
4407 #define R_2P4G_BAND 0x4970
4409 #define R_FC0_BW 0x4974
4410 #define R_FC0_BW_V1 0x49C0
4415 #define B_FC0_BW_INV GENMASK(6, 0)
4416 #define R_CHBW_MOD 0x4978
4417 #define R_CHBW_MOD_V1 0x49C4
4421 #define B_ANT_RX_SEG0 GENMASK(3, 0)
4422 #define R_P0_RPL1 0x49B0
4428 #define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
4429 #define R_P0_RPL2 0x49B4
4433 #define B_P0_RTL2_42_MASK GENMASK(7, 0)
4434 #define R_P0_RPL3 0x49B8
4438 #define B_P0_RTL3_82_MASK GENMASK(7, 0)
4439 #define R_PD_BOOST_EN 0x49E8
4441 #define R_P1_BACKOFF_IBADC_V1 0x49F0
4443 #define R_P1_RPL1 0x4A00
4444 #define R_P1_RPL2 0x4A04
4445 #define R_P1_RPL3 0x4A08
4446 #define R_BK_FC0_INV_V1 0x4A1C
4447 #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
4448 #define R_CCK_FC0_INV_V1 0x4A20
4449 #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
4450 #define R_PATH1_RXB_INIT_V1 0x4A5C
4452 #define R_P1_AGC_CTL 0x4A9C
4454 #define R_PATH1_TIA_INIT_V1 0x4AA8
4456 #define R_P0_AGC_RSVD 0x4ACC
4457 #define R_PATH0_RXBB_V1 0x4AD4
4458 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
4459 #define R_P1_AGC_RSVD 0x4AD8
4460 #define R_PATH1_RXBB_V1 0x4AE0
4461 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
4462 #define R_PATH0_BT_BACKOFF_V1 0x4AE4
4463 #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
4464 #define R_PATH1_BT_BACKOFF_V1 0x4AEC
4465 #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
4466 #define R_DCFO_COMP_S0_V2 0x4B20
4467 #define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0)
4468 #define R_PATH0_TX_CFR 0x4B30
4470 #define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)
4471 #define R_PATH0_TX_POLAR_CLIPPING 0x4B3C
4474 #define R_PATH0_FRC_FIR_TYPE_V1 0x4C00
4475 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
4476 #define R_PATH0_NOTCH 0x4C14
4478 #define B_PATH0_NOTCH_VAL GENMASK(11, 0)
4479 #define R_PATH0_NOTCH2 0x4C20
4481 #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
4482 #define R_PATH0_5MDET 0x4C4C
4483 #define R_PATH0_5MDET_V1 0x46F8
4487 #define B_PATH0_5MDET_TH GENMASK(5, 0)
4488 #define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4
4489 #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
4490 #define R_PATH1_NOTCH 0x4CD8
4492 #define B_PATH1_NOTCH_VAL GENMASK(11, 0)
4493 #define R_PATH1_NOTCH2 0x4CE4
4495 #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
4496 #define R_PATH1_5MDET 0x4D10
4497 #define R_PATH1_5MDET_V1 0x47B8
4501 #define B_PATH1_5MDET_TH GENMASK(5, 0)
4502 #define R_RPL_BIAS_COMP 0x4DF0
4503 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
4504 #define R_RPL_PATHAB 0x4E0C
4507 #define R_RSSI_M_PATHAB 0x4E2C
4509 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
4510 #define R_FC0_V1 0x4E30
4511 #define B_FC0_MSK_V1 GENMASK(12, 0)
4512 #define R_RX_BW40_2XFFT_EN_V1 0x4E30
4514 #define R_DCFO_COMP_S0_V1 0x4A40
4515 #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
4516 #define R_BMODE_PDTH_V1 0x4B64
4517 #define R_BMODE_PDTH_V2 0x6708
4519 #define R_BMODE_PDTH_EN_V1 0x4B74
4520 #define R_BMODE_PDTH_EN_V2 0x6718
4522 #define R_CFO_COMP_SEG1_L 0x5384
4523 #define R_CFO_COMP_SEG1_H 0x5388
4524 #define R_CFO_COMP_SEG1_CTRL 0x538C
4527 #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
4528 #define R_TSSI_PA_K1 0x5600
4529 #define R_TSSI_PA_K2 0x5604
4530 #define R_P0_TSSI_ALIM1 0x5630
4531 #define B_P0_TSSI_ALIM1 GENMASK(29, 0)
4534 #define B_P0_TSSI_ALIM13 GENMASK(9, 0)
4535 #define R_P0_TSSI_ALIM3 0x5634
4536 #define B_P0_TSSI_ALIM31 GENMASK(9, 0)
4537 #define R_TSSI_PA_K5 0x5638
4538 #define R_P0_TSSI_ALIM2 0x563c
4539 #define B_P0_TSSI_ALIM2 GENMASK(29, 0)
4540 #define R_P0_TSSI_ALIM4 0x5640
4541 #define R_TSSI_PA_K8 0x5644
4542 #define R_UPD_CLK 0x5670
4548 #define R_TXPWRB 0x56CC
4551 #define R_DPD_OFT_EN 0x5800
4555 #define B_DPD_REF GENMASK(8, 0)
4556 #define R_P0_TSSIC 0x5814
4558 #define R_DPD_OFT_ADDR 0x5804
4560 #define R_TXPWRB_H 0x580c
4562 #define R_P0_TMETER 0x5810
4566 #define R_P1_TSSIC 0x7814
4568 #define R_P0_TSSI_TRK 0x5818
4572 #define B_P0_TSSI_OFT GENMASK(7, 0)
4573 #define R_P0_TSSI_AVG 0x5820
4576 #define R_P0_RFCTM 0x5864
4580 #define R_P0_TRSW 0x5868
4585 #define B_P0_TRSW_B BIT(0)
4586 #define B_P0_ANT_TRAIN_EN BIT(0)
4588 #define R_P0_ANTSEL 0x586C
4597 #define R_RFSW_CTRL_ANT0_BASE 0x5870
4598 #define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0)
4599 #define R_RFE_SEL0_BASE 0x5880
4600 #define B_RFE_SEL0_SRC_MASK GENMASK(3, 0)
4601 #define R_RFE_SEL32_BASE 0x5884
4603 #define R_RFE_INV0 0x5890
4604 #define R_P0_RFM 0x5894
4608 #define B_P0_RFM_OUT GENMASK(4, 0)
4609 #define R_P0_PATH_RST 0x58AC
4610 #define R_P0_TXDPD 0x58D4
4612 #define R_P0_TXPW_RSTB 0x58DC
4615 #define R_P0_TSSI_MV_AVG 0x58E4
4619 #define R_TXGAIN_SCALE 0x58F0
4622 #define R_P0_TSSI_BASE 0x5C00
4623 #define R_S0_DACKI 0x5E00
4626 #define R_S0_DACKI2 0x5E30
4628 #define R_S0_DACKI7 0x5E44
4630 #define R_S0_DACKI8 0x5E48
4632 #define R_S0_DACKQ 0x5E50
4635 #define R_S0_DACKQ2 0x5E80
4637 #define R_S0_DACKQ7 0x5E94
4639 #define R_S0_DACKQ8 0x5E98
4641 #define R_RPL_BIAS_COMP1 0x6DF0
4642 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
4643 #define R_P1_TSSI_ALIM1 0x7630
4644 #define B_P1_TSSI_ALIM1 GENMASK(29, 0)
4647 #define B_P1_TSSI_ALIM13 GENMASK(9, 0)
4648 #define R_P1_TSSI_ALIM3 0x7634
4649 #define B_P1_TSSI_ALIM31 GENMASK(9, 0)
4650 #define R_P1_TSSI_ALIM2 0x763c
4651 #define B_P1_TSSI_ALIM2 GENMASK(29, 0)
4652 #define R_P1_TSSIC 0x7814
4654 #define R_P1_TMETER 0x7810
4658 #define R_P1_TSSI_TRK 0x7818
4662 #define B_P1_TSSI_OFT GENMASK(7, 0)
4663 #define R_P1_TSSI_AVG 0x7820
4666 #define R_P1_RFCTM 0x7864
4670 #define R_P1_PATH_RST 0x78AC
4671 #define R_P1_TXPW_RSTB 0x78DC
4674 #define R_P1_TSSI_MV_AVG 0x78E4
4678 #define R_TSSI_THOF 0x7C00
4679 #define R_S1_DACKI 0x7E00
4682 #define R_S1_DACKI2 0x7E30
4684 #define R_S1_DACKI7 0x7E44
4686 #define R_S1_DACKI8 0x7E48
4688 #define R_S1_DACKQ 0x7E50
4691 #define R_S1_DACKQ2 0x7E80
4693 #define R_S1_DACKQ7 0x7E94
4695 #define R_S1_DACKQ8 0x7E98
4697 #define R_NCTL_CFG 0x8000
4699 #define R_NCTL_RPT 0x8008
4701 #define R_NCTL_N1 0x8010
4702 #define B_NCTL_N1_CIP GENMASK(7, 0)
4703 #define R_NCTL_N2 0x8014
4704 #define R_IQK_COM 0x8018
4705 #define R_IQK_DIF 0x801C
4706 #define B_IQK_DIF_TRX GENMASK(1, 0)
4707 #define R_IQK_DIF1 0x8020
4708 #define B_IQK_DIF1_TXPI GENMASK(19, 0)
4709 #define R_IQK_DIF2 0x8024
4710 #define B_IQK_DIF2_RXPI GENMASK(19, 0)
4711 #define R_IQK_DIF4 0x802C
4713 #define B_IQK_DIF4_TXT GENMASK(11, 0)
4714 #define IQK_DF4_TXT_8_25MHZ 0x021
4715 #define R_IQK_CFG 0x8034
4717 #define R_IQK_RXA 0x8044
4719 #define R_TPG_SEL 0x8068
4720 #define R_TPG_MOD 0x806C
4722 #define R_MDPK_SYNC 0x8070
4726 #define R_MDPK_RX_DCK 0x8074
4728 #define R_KIP_MOD 0x8078
4729 #define B_KIP_MOD GENMASK(19, 0)
4730 #define R_NCTL_RW 0x8080
4731 #define R_KIP_SYSCFG 0x8088
4732 #define R_KIP_CLK 0x808C
4733 #define R_DPK_IDL 0x809C
4736 #define R_LDL_NORM 0x80A0
4739 #define B_LDL_NORM_OP GENMASK(1, 0)
4740 #define R_DPK_CTL 0x80B0
4742 #define R_DPK_CFG 0x80B8
4744 #define R_DPK_CFG2 0x80BC
4746 #define R_DPK_CFG3 0x80C0
4747 #define R_KPATH_CFG 0x80D0
4749 #define R_KIP_RPT1 0x80D4
4752 #define R_SRAM_IQRX 0x80D8
4753 #define R_IDL_MPA 0x80DC
4756 #define B_IDL_MD500 BIT(0)
4757 #define R_GAPK 0x80E0
4758 #define B_GAPK_ADR BIT(0)
4759 #define R_SRAM_IQRX2 0x80E8
4760 #define R_DPK_MPA 0x80EC
4764 #define R_DPK_WR 0x80F4
4766 #define R_DPK_TRK 0x80f0
4768 #define R_RPT_COM 0x80FC
4772 #define B_RPT_COM_RDY GENMASK(15, 0)
4773 #define B_PRT_COM_DCQ GENMASK(11, 0)
4776 #define B_PRT_COM_CORI GENMASK(7, 0)
4777 #define B_PRT_COM_RXBB GENMASK(5, 0)
4778 #define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
4779 #define B_PRT_COM_DONE BIT(0)
4780 #define R_COEF_SEL 0x8104
4781 #define B_COEF_SEL_IQC BIT(0)
4783 #define R_CFIR_SYS 0x8120
4784 #define R_IQK_RES 0x8124
4787 #define B_IQK_RES_RXCFIR GENMASK(3, 0)
4788 #define R_TXIQC 0x8138
4789 #define R_RXIQC 0x813c
4790 #define B_RXIQC_BYPASS BIT(0)
4794 #define R_KIP 0x8140
4795 #define B_KIP_DBCC BIT(0)
4797 #define R_RFGAIN 0x8144
4798 #define B_RFGAIN_PAD GENMASK(4, 0)
4800 #define R_RFGAIN_BND 0x8148
4801 #define B_RFGAIN_BND GENMASK(4, 0)
4802 #define R_CFIR_MAP 0x8150
4803 #define R_CFIR_LUT 0x8154
4808 #define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
4809 #define B_CFIR_LUT_GP GENMASK(1, 0)
4810 #define R_DPK_GN 0x819C
4812 #define B_DPK_GN_AG GENMASK(9, 0)
4813 #define R_DPD_V1 0x81a0
4815 #define R_DPD_CH0 0x81AC
4816 #define R_DPD_BND 0x81B4
4818 #define B_DPD_BND_0 GENMASK(8, 0)
4819 #define R_DPD_CH0A 0x81BC
4823 #define B_DPD_CFG GENMASK(22, 0)
4825 #define R_TXAGC_RFK 0x81C4
4826 #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
4827 #define R_DPD_COM 0x81C8
4829 #define R_KIP_IQP 0x81CC
4831 #define B_KIP_IQP_IQSW GENMASK(5, 0)
4832 #define R_KIP_RPT 0x81D4
4834 #define R_W_COEF 0x81D8
4835 #define R_LOAD_COEF 0x81DC
4837 #define B_LOAD_COEF_CFIR GENMASK(1, 0)
4839 #define B_LOAD_COEF_AUTO BIT(0)
4840 #define R_DPK_GL 0x81F0
4842 #define B_DPK_GL_A1 GENMASK(17, 0)
4843 #define R_RPT_PER 0x81FC
4847 #define B_RPT_PER_TH GENMASK(5, 0)
4848 #define R_IQRSN 0x8220
4851 #define R_RXCFIR_P0C0 0x8D40
4852 #define R_RXCFIR_P0C1 0x8D84
4853 #define R_RXCFIR_P0C2 0x8DC8
4854 #define R_RXCFIR_P0C3 0x8E0C
4855 #define R_TXCFIR_P0C0 0x8F50
4856 #define R_TXCFIR_P0C1 0x8F84
4857 #define R_TXCFIR_P0C2 0x8FB8
4858 #define R_TXCFIR_P0C3 0x8FEC
4859 #define R_RXCFIR_P1C0 0x9140
4860 #define R_RXCFIR_P1C1 0x9184
4861 #define R_RXCFIR_P1C2 0x91C8
4862 #define R_RXCFIR_P1C3 0x920C
4863 #define R_TXCFIR_P1C0 0x9350
4864 #define R_TXCFIR_P1C1 0x9384
4865 #define R_TXCFIR_P1C2 0x93B8
4866 #define R_TXCFIR_P1C3 0x93EC
4867 #define R_IQKINF 0x9FE0
4871 #define B_IQKINF_FAIL GENMASK(3, 0)
4875 #define B_IQKINF_FCOR BIT(0)
4876 #define R_IQKCH 0x9FE4
4879 #define B_IQKCH_BAND GENMASK(3, 0)
4880 #define R_IQKINF2 0x9FE8
4883 #define B_IQKINF2_NCTLV GENMASK(7, 0)
4884 #define R_DCOF0 0xC000
4887 #define R_DCOF1 0xC004
4889 #define B_DCOF1_S BIT(0)
4890 #define R_DCOF8 0xC020
4892 #define R_DCOF9 0xC024
4894 #define R_DACK_S0P0 0xC040
4896 #define R_DACK_BIAS00 0xc048
4898 #define R_DACK_S0P2 0xC05C
4901 #define R_DACK_DADCK00 0xC060
4903 #define R_DACK_S0P1 0xC064
4905 #define R_DACK_BIAS01 0xC06C
4907 #define R_DACK_S0P3 0xC080
4910 #define R_DACK_DADCK01 0xC084
4912 #define R_DRCK_FH 0xC094
4914 #define R_DRCK 0xC0C4
4918 #define B_DRCK_VAL GENMASK(4, 0)
4919 #define R_DRCK_RES 0xC0C8
4922 #define R_DRCK_V1 0xC0CC
4925 #define B_DRCK_V1_CV GENMASK(4, 0)
4926 #define R_DRCK_RS 0xC0D0
4929 #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
4931 #define R_P0_CFCH_BW0 0xC0D4
4935 #define R_P0_CFCH_BW1 0xC0D8
4938 #define R_WDADC 0xC0E4
4940 #define R_ADCMOD 0xC0E8
4942 #define R_DCIM 0xC0EC
4944 #define R_ADDCK0D 0xC0F0
4948 #define R_ADDCK0 0xC0F4
4954 #define B_ADDCK0_VAL GENMASK(3, 0)
4956 #define R_ADDCK0_RL 0xC0F8
4960 #define R_ADDCKR0 0xC0FC
4963 #define B_ADDCKR0_A1 GENMASK(9, 0)
4964 #define R_DACK10 0xC100
4966 #define R_DACK1_K 0xc104
4967 #define B_DACK1_EN BIT(0)
4968 #define R_DACK11 0xC120
4970 #define R_DACK_S1P0 0xC140
4972 #define R_DACK_BIAS10 0xC148
4974 #define R_DACK10S 0xC15C
4976 #define R_DACK_S1P2 0xC15C
4978 #define R_DACK_DADCK10 0xC160
4980 #define R_DACK_S1P1 0xC164
4982 #define R_DACK_BIAS11 0xC16C
4984 #define R_DACK11S 0xC180
4986 #define R_DACK_S1P3 0xC180
4988 #define R_DACK_DADCK11 0xC184
4990 #define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
4992 #define R_PATH0_BW_SEL_V1 0xC0D8
4994 #define R_PATH1_BW_SEL_V1 0xC1D8
4997 #define R_ADDCK1D 0xC1F0
5000 #define R_ADDCK1 0xC1F4
5006 #define R_ADDCK1_RL 0xC1F8
5010 #define R_ADDCKR1 0xC1fC
5012 #define B_ADDCKR1_A1 GENMASK(9, 0)
5013 #define R_DACKN0_CTL 0xC210
5014 #define B_DACKN0_EN BIT(0)
5016 #define R_DACKN1_CTL 0xC224
5020 #define R_AX_WDT_CTRL 0x0040
5027 #define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
5028 #define WDT_CTRL_ALL_DIS 0
5030 #define R_AX_WDT_STATUS 0x0044
5032 #define B_AX_FS_WDT_INT_MSK BIT(0)