Lines Matching +full:12 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8821cu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8821cs_efuse_parsing()
50 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_read_efuse()
51 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
57 efuse->rfe_option = map->rfe_option & 0x1f; in rtw8821c_read_efuse()
58 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
59 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
60 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
61 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
62 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
63 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
64 efuse->channel_plan = map->channel_plan; in rtw8821c_read_efuse()
65 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
66 efuse->country_code[1] = map->country_code[1]; in rtw8821c_read_efuse()
67 efuse->bt_setting = map->rf_bt_setting; in rtw8821c_read_efuse()
68 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
69 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
70 efuse->thermal_meter_k = map->thermal_meter; in rtw8821c_read_efuse()
71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; in rtw8821c_read_efuse()
72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; in rtw8821c_read_efuse()
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
76 switch (efuse->rfe_option) { in rtw8821c_read_efuse()
83 hal->rfe_btg = true; in rtw8821c_read_efuse()
88 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; in rtw8821c_read_efuse()
90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) in rtw8821c_read_efuse()
91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; in rtw8821c_read_efuse()
105 return -ENOTSUPP; in rtw8821c_read_efuse()
135 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_init()
139 dm_info->default_ofdm_index = 24; in rtw8821c_pwrtrack_init()
141 dm_info->default_ofdm_index = swing_idx; in rtw8821c_pwrtrack_init()
143 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); in rtw8821c_pwrtrack_init()
144 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
145 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
146 dm_info->pwr_trk_triggered = false; in rtw8821c_pwrtrack_init()
147 dm_info->pwr_trk_init_trigger = true; in rtw8821c_pwrtrack_init()
148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8821c_pwrtrack_init()
160 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_phy_set_param()
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); in rtw8821c_phy_set_param()
197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); in rtw8821c_phy_set_param()
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
241 /* Set beacon cotnrol - enable TSF and other related functions */ in rtw8821c_mac_init()
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
312 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_channel_rf()
344 if (hal->rfe_btg) in rtw8821c_set_channel_rf()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
387 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_channel_bb()
391 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
392 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
393 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
404 hal->ch_param[0]); in rtw8821c_set_channel_bb()
406 hal->ch_param[1] & MASKLWORD); in rtw8821c_set_channel_bb()
408 hal->ch_param[2]); in rtw8821c_set_channel_bb()
411 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
412 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
413 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
441 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
445 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
447 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
455 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
464 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
472 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
473 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
481 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
482 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
489 struct rtw_efuse efuse = rtwdev->efuse; in rtw8821c_get_bb_swing()
521 struct rtw_efuse *efuse = &rtwdev->efuse; in get_cck_rx_pwr()
527 if (efuse->rfe_option == 0) { in get_cck_rx_pwr()
537 return -120; in get_cck_rx_pwr()
541 rx_pwr_all = lna_gain - 2 * vga_idx; in get_cck_rx_pwr()
549 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page0()
559 pkt_stat->rx_power[RF_PATH_A] = rx_power; in query_phy_status_page0()
560 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page0()
561 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page0()
562 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; in query_phy_status_page0()
563 pkt_stat->signal_power = rx_power; in query_phy_status_page0()
569 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page1()
571 s8 min_rx_power = -120; in query_phy_status_page1()
573 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) in query_phy_status_page1()
580 else if (rxsc >= 9 && rxsc <= 12) in query_phy_status_page1()
587 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; in query_phy_status_page1()
588 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page1()
589 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page1()
590 pkt_stat->bw = bw; in query_phy_status_page1()
591 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page1()
620 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; in rtw8821c_query_rx_desc()
625 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); in rtw8821c_query_rx_desc()
626 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); in rtw8821c_query_rx_desc()
627 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); in rtw8821c_query_rx_desc()
628 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && in rtw8821c_query_rx_desc()
630 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); in rtw8821c_query_rx_desc()
631 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); in rtw8821c_query_rx_desc()
632 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); in rtw8821c_query_rx_desc()
633 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); in rtw8821c_query_rx_desc()
634 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); in rtw8821c_query_rx_desc()
635 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); in rtw8821c_query_rx_desc()
636 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); in rtw8821c_query_rx_desc()
637 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); in rtw8821c_query_rx_desc()
639 /* drv_info_sz is in unit of 8-bytes */ in rtw8821c_query_rx_desc()
640 pkt_stat->drv_info_sz *= 8; in rtw8821c_query_rx_desc()
643 if (pkt_stat->is_c2h) in rtw8821c_query_rx_desc()
646 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + in rtw8821c_query_rx_desc()
647 pkt_stat->drv_info_sz); in rtw8821c_query_rx_desc()
648 if (pkt_stat->phy_status) { in rtw8821c_query_rx_desc()
649 phy_status = rx_desc + desc_sz + pkt_stat->shift; in rtw8821c_query_rx_desc()
659 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index_by_rate()
667 pwr_index = hal->tx_pwr_tbl[path][rate]; in rtw8821c_set_tx_power_index_by_rate()
681 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index()
684 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
696 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_false_alarm_statistics()
703 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
707 dm_info->cck_fa_cnt = cck_fa_cnt; in rtw8821c_false_alarm_statistics()
708 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
709 dm_info->total_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
711 dm_info->total_fa_cnt += cck_fa_cnt; in rtw8821c_false_alarm_statistics()
714 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
715 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
718 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
719 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
722 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
723 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
726 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
727 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
730 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); in rtw8821c_false_alarm_statistics()
731 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; in rtw8821c_false_alarm_statistics()
734 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
735 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; in rtw8821c_false_alarm_statistics()
738 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
739 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
740 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
741 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
742 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
743 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
767 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); in rtw8821c_do_iqk()
791 /* enable PTA (3-wire function form BT side) */ in rtw8821c_coex_cfg_init()
802 /* beacon queue always hi-pri */ in rtw8821c_coex_cfg_init()
810 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_ant_switch()
811 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_ant_switch()
812 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_ant_switch()
817 if (switch_status == coex_dm->cur_switch_status) in rtw8821c_coex_cfg_ant_switch()
820 if (coex_rfe->wlg_at_btg) { in rtw8821c_coex_cfg_ant_switch()
823 if (coex_rfe->ant_switch_polarity) in rtw8821c_coex_cfg_ant_switch()
829 coex_dm->cur_switch_status = switch_status; in rtw8821c_coex_cfg_ant_switch()
831 if (coex_rfe->ant_switch_diversity && in rtw8821c_coex_cfg_ant_switch()
835 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); in rtw8821c_coex_cfg_ant_switch()
847 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
848 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
919 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_rfe_type()
920 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_rfe_type()
921 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_rfe_type()
923 coex_rfe->rfe_module_type = efuse->rfe_option; in rtw8821c_coex_cfg_rfe_type()
924 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
925 coex_rfe->ant_switch_exist = true; in rtw8821c_coex_cfg_rfe_type()
926 coex_rfe->wlg_at_btg = false; in rtw8821c_coex_cfg_rfe_type()
928 switch (coex_rfe->rfe_module_type) { in rtw8821c_coex_cfg_rfe_type()
932 case 9: /* 1-Ant, Main, WLG */ in rtw8821c_coex_cfg_rfe_type()
933 default: /* 2-Ant, DPDT, WLG */ in rtw8821c_coex_cfg_rfe_type()
936 case 10: /* 1-Ant, Main, BTG */ in rtw8821c_coex_cfg_rfe_type()
938 case 15: /* 2-Ant, DPDT, BTG */ in rtw8821c_coex_cfg_rfe_type()
939 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
942 case 11: /* 1-Ant, Aux, WLG */ in rtw8821c_coex_cfg_rfe_type()
943 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
946 case 12: /* 1-Ant, Aux, BTG */ in rtw8821c_coex_cfg_rfe_type()
947 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
948 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
951 case 13: /* 2-Ant, no switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
953 case 14: /* 2-Ant, no antenna switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
954 coex_rfe->ant_switch_exist = false; in rtw8821c_coex_cfg_rfe_type()
961 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_wl_tx_power()
962 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_wl_tx_power()
963 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_wl_tx_power()
964 bool share_ant = efuse->share_ant; in rtw8821c_coex_cfg_wl_tx_power()
969 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) in rtw8821c_coex_cfg_wl_tx_power()
972 coex_dm->cur_wl_pwr_lvl = wl_pwr; in rtw8821c_coex_cfg_wl_tx_power()
983 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_txagc_swing_offset()
984 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_txagc_swing_offset()
985 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; in rtw8821c_txagc_swing_offset()
989 u8 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
992 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); in rtw8821c_txagc_swing_offset()
997 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1000 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
1001 delta_pwr_idx - pwr_idx_offset; in rtw8821c_txagc_swing_offset()
1007 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1009 if (dm_info->default_ofdm_index > in rtw8821c_txagc_swing_offset()
1010 (pwr_idx_offset_lower - delta_pwr_idx)) in rtw8821c_txagc_swing_offset()
1011 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
1012 delta_pwr_idx - pwr_idx_offset_lower; in rtw8821c_txagc_swing_offset()
1022 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; in rtw8821c_txagc_swing_offset()
1044 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_set()
1047 u8 channel = rtwdev->hal.current_channel; in rtw8821c_pwrtrack_set()
1048 u8 band_width = rtwdev->hal.current_band_width; in rtw8821c_pwrtrack_set()
1050 u8 tx_rate = dm_info->tx_rate; in rtw8821c_pwrtrack_set()
1051 u8 max_pwr_idx = rtwdev->chip->max_power_index; in rtw8821c_pwrtrack_set()
1058 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1059 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1066 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_pwrtrack()
1072 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
1079 if (dm_info->pwr_trk_init_trigger) in rtw8821c_phy_pwrtrack()
1080 dm_info->pwr_trk_init_trigger = false; in rtw8821c_phy_pwrtrack()
1087 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw8821c_phy_pwrtrack()
1089 dm_info->delta_power_index[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1092 if (dm_info->delta_power_index[RF_PATH_A] == in rtw8821c_phy_pwrtrack()
1093 dm_info->delta_power_index_last[RF_PATH_A]) in rtw8821c_phy_pwrtrack()
1096 dm_info->delta_power_index_last[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1097 dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_phy_pwrtrack()
1107 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_pwr_track()
1108 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwr_track()
1110 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
1113 if (!dm_info->pwr_trk_triggered) { in rtw8821c_pwr_track()
1116 dm_info->pwr_trk_triggered = true; in rtw8821c_pwr_track()
1121 dm_info->pwr_trk_triggered = false; in rtw8821c_pwr_track()
1147 if (bfee->role == RTW_BFEE_SU) in rtw8821c_bf_config_bfee()
1149 else if (bfee->role == RTW_BFEE_MU) in rtw8821c_bf_config_bfee()
1157 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_cck_pd_set()
1161 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", in rtw8821c_phy_cck_pd_set()
1162 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); in rtw8821c_phy_cck_pd_set()
1164 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) in rtw8821c_phy_cck_pd_set()
1172 dm_info->cck_pd_default + new_lvl * 2, in rtw8821c_phy_cck_pd_set()
1173 pd[new_lvl], dm_info->cck_fa_avg); in rtw8821c_phy_cck_pd_set()
1175 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw8821c_phy_cck_pd_set()
1177 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; in rtw8821c_phy_cck_pd_set()
1180 dm_info->cck_pd_default + new_lvl * 2); in rtw8821c_phy_cck_pd_set()
1195 RTW_PWR_CMD_WRITE, BIT(0), 0},
1200 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1205 RTW_PWR_CMD_WRITE, BIT(0), 0},
1210 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1233 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1243 RTW_PWR_CMD_WRITE, BIT(5), 0},
1248 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1253 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1258 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1263 RTW_PWR_CMD_WRITE, BIT(0), 0},
1268 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1273 RTW_PWR_CMD_WRITE, BIT(7), 0},
1278 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1283 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1288 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1293 RTW_PWR_CMD_POLLING, BIT(0), 0},
1298 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1303 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1308 RTW_PWR_CMD_WRITE, BIT(1), 0},
1313 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1314 (BIT(7) | BIT(6) | BIT(5))},
1319 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1324 RTW_PWR_CMD_WRITE, BIT(1), 0},
1337 RTW_PWR_CMD_WRITE, BIT(3), 0},
1347 RTW_PWR_CMD_WRITE, BIT(1), 0},
1352 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1357 RTW_PWR_CMD_WRITE, BIT(1), 0},
1362 RTW_PWR_CMD_WRITE, BIT(0), 0},
1367 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1372 RTW_PWR_CMD_POLLING, BIT(1), 0},
1377 RTW_PWR_CMD_WRITE, BIT(3), 0},
1382 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1400 RTW_PWR_CMD_WRITE, BIT(5), 0},
1405 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1410 RTW_PWR_CMD_WRITE, BIT(0), 0},
1415 RTW_PWR_CMD_WRITE, BIT(5), 0},
1420 RTW_PWR_CMD_WRITE, BIT(4), 0},
1425 RTW_PWR_CMD_WRITE, BIT(0), 0},
1430 RTW_PWR_CMD_WRITE, BIT(1), 0},
1435 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1440 RTW_PWR_CMD_WRITE, BIT(2), 0},
1445 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1450 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1455 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1460 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1465 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1470 RTW_PWR_CMD_POLLING, BIT(1), 0},
1475 RTW_PWR_CMD_WRITE, BIT(1), 0},
1648 /* rssi in percentage % (dbm = % - 100) */
1652 /* Shared-Antenna Coex Table */
1654 {0x55555555, 0x55555555}, /* case-0 */
1659 {0xfafafafa, 0xfafafafa}, /* case-5 */
1664 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1669 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1674 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1679 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1684 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1689 /* Non-Shared-Antenna Coex Table */
1691 {0xffffffff, 0xffffffff}, /* case-100 */
1696 {0xffffffff, 0xffffffff}, /* case-105 */
1701 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1706 {0xffff55ff, 0xffff55ff}, /* case-115 */
1711 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1717 /* Shared-Antenna TDMA */
1719 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1720 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1724 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1729 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1734 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1739 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1744 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1749 /* Non-Shared-Antenna TDMA */
1751 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1756 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1761 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1766 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1771 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1780 {0, 20, false, 7}, /* for WL-CPT */
1789 {0, 20, false, 7}, /* for WL-CPT */
1800 11, 11, 12, 12, 12, 12, 12},
1802 11, 12, 12, 12, 12, 12, 12, 12},
1804 11, 12, 12, 12, 12, 12, 12},
1809 12, 12, 12, 12, 12, 12, 12},
1811 12, 12, 12, 12, 12, 12, 12, 12},
1813 11, 12, 12, 12, 12, 12, 12, 12},
1818 11, 11, 12, 12, 12, 12, 12},
1820 11, 12, 12, 12, 12, 12, 12, 12},
1822 11, 12, 12, 12, 12, 12, 12},
1827 12, 12, 12, 12, 12, 12, 12},
1829 12, 12, 12, 12, 12, 12, 12, 12},
1831 11, 12, 12, 12, 12, 12, 12, 12},
1906 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1909 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1910 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1911 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1912 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1917 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1946 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),