Lines Matching +full:0 +full:x0a60
20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
45 u8 res4[48]; /* 0xd0 */
46 u8 vender_id[2]; /* 0x100 */
47 u8 product_id[2]; /* 0x102 */
48 u8 usb_option; /* 0x104 */
49 u8 res5[2]; /* 0x105 */
50 u8 mac_addr[ETH_ALEN]; /* 0x107 */
54 u8 res4[0x4a]; /* 0xd0 */
55 u8 mac_addr[ETH_ALEN]; /* 0x11a */
67 u8 channel_plan; /* 0xb8 */
71 u8 pa_type; /* 0xbc */
72 u8 lna_type_2g[2]; /* 0xbd */
82 u8 rf_antenna_option; /* 0xc9 */
97 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
101 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
103 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
105 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
107 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
109 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
111 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
113 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
115 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
130 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ in iqk_mult()
135 #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing)
143 #define IQK_TX_X_ERR 0x142
144 #define IQK_TX_Y_ERR 0x42
145 #define IQK_RX_X_UPPER 0x11a
146 #define IQK_RX_X_LOWER 0xe6
147 #define IQK_RX_Y_LMT 0x1a
148 #define IQK_TX_OK BIT(0)
152 #define SPUR_THRES 0x16
154 #define DIS_3WIRE 0xccf000c0
155 #define EN_3WIRE 0xccc000c0
156 #define START_PSD 0x400000
157 #define FREQ_CH13 0xfccd
158 #define FREQ_CH14 0xff9a
159 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)
163 #define BIT_MASK_RFMOD BIT(0)
166 #define REG_GPIO_INTM 0x0048
167 #define REG_BTG_SEL 0x0067
169 #define REG_LTECOEX_PATH_CONTROL 0x0070
170 #define REG_LTECOEX_CTRL 0x07c0
171 #define REG_LTECOEX_WRITE_DATA 0x07c4
172 #define REG_LTECOEX_READ_DATA 0x07c8
173 #define REG_PSDFN 0x0808
174 #define REG_BB_PWR_SAV1_11N 0x0874
175 #define REG_ANA_PARAM1 0x0880
176 #define REG_ANALOG_P4 0x088c
177 #define REG_PSDRPT 0x08b4
178 #define REG_FPGA1_RFMOD 0x0900
179 #define REG_BB_SEL_BTG 0x0948
180 #define REG_BBRX_DFIR 0x0954
183 #define REG_CCK0_SYS 0x0a00
185 #define REG_CCK_ANT_SEL_11N 0x0a04
186 #define REG_PWRTH 0x0a08
187 #define REG_CCK_FA_RST_11N 0x0a2c
194 #define REG_CCK_FA_LSB_11N 0x0a5c
195 #define REG_CCK_FA_MSB_11N 0x0a58
196 #define REG_CCK_CCA_CNT_11N 0x0a60
197 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
199 #define REG_PWRTH2 0x0aa8
200 #define REG_CSRATIO 0x0aaa
201 #define REG_OFDM_FA_HOLDC_11N 0x0c00
203 #define REG_BB_RX_PATH_11N 0x0c04
204 #define REG_TRMUX_11N 0x0c08
205 #define REG_OFDM_FA_RSTC_11N 0x0c0c
207 #define REG_A_RXIQI 0x0c14
208 #define BIT_MASK_RXIQ_S1_X 0x000003FF
209 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00
210 #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F)
211 #define REG_OFDM0_RXDSP 0x0c40
214 #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c
219 #define REG_OFDM0_XAAGC1 0x0c50
220 #define REG_OFDM0_XBAGC1 0x0c58
221 #define REG_AGCRSSI 0x0c78
222 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80
223 #define BIT_MASK_TXIQ_ELM_A 0x03ff
224 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \
225 ((a) & 0x03ff))
227 #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F)
229 #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94
230 #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6)
231 #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0
232 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000
233 #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF)
234 #define REG_TXIQ_AB_S0 0x0cd0
235 #define BIT_MASK_TXIQ_A_S0 0x000007FE
236 #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0)
237 #define BIT_MASK_TXIQ_B_S0 0x0007E000
238 #define REG_TXIQ_CD_S0 0x0cd4
239 #define BIT_MASK_TXIQ_C_S0 0x000007FE
240 #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0)
243 #define REG_RXIQ_AB_S0 0x0cd8
244 #define BIT_MASK_RXIQ_X_S0 0x000003FF
245 #define BIT_MASK_RXIQ_Y_S0 0x003FF000
246 #define REG_OFDM_FA_TYPE1_11N 0x0cf0
247 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)
249 #define REG_OFDM_FA_RSTD_11N 0x0d00
252 #define REG_CTX 0x0d03
254 #define REG_OFDM1_CFOTRK 0x0d2c
256 #define REG_OFDM1_CSI1 0x0d40
257 #define REG_OFDM1_CSI2 0x0d44
258 #define REG_OFDM1_CSI3 0x0d48
259 #define REG_OFDM1_CSI4 0x0d4c
260 #define REG_OFDM_FA_TYPE2_11N 0x0da0
261 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)
263 #define REG_OFDM_FA_TYPE3_11N 0x0da4
264 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)
266 #define REG_OFDM_FA_TYPE4_11N 0x0da8
267 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)
268 #define REG_FPGA0_IQK_11N 0x0e28
269 #define BIT_MASK_IQK_MOD 0xffffff00
270 #define EN_IQK 0x808000
271 #define RST_IQK 0x000000
272 #define REG_TXIQK_TONE_A_11N 0x0e30
273 #define REG_RXIQK_TONE_A_11N 0x0e34
274 #define REG_TXIQK_PI_A_11N 0x0e38
275 #define REG_RXIQK_PI_A_11N 0x0e3c
276 #define REG_TXIQK_11N 0x0e40
277 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y))
278 #define REG_RXIQK_11N 0x0e44
279 #define REG_IQK_AGC_PTS_11N 0x0e48
280 #define REG_IQK_AGC_RSP_11N 0x0e4c
281 #define REG_TX_IQK_TONE_B 0x0e50
282 #define REG_RX_IQK_TONE_B 0x0e54
283 #define REG_IQK_RES_TX 0x0e94
285 #define REG_IQK_RES_TY 0x0e9c
287 #define REG_IQK_RES_RX 0x0ea4
289 #define REG_IQK_RES_RY 0x0eac
294 #define REG_PAGE_F_RST_11N 0x0f14
296 #define REG_IGI_C_11N 0x0f84
297 #define REG_IGI_D_11N 0x0f88
298 #define REG_HT_CRC32_CNT_11N 0x0f90
299 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0)
301 #define REG_OFDM_CRC32_CNT_11N 0x0f94
302 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)
304 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8