Lines Matching +full:0 +full:xe94
19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 },
20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 },
21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 },
22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 },
23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff },
24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 },
25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 },
26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 },
27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff },
28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 },
29 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 },
30 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 },
31 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff },
32 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 },
33 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 },
34 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 },
35 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff },
36 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 },
37 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 },
38 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 },
41 #define WLAN_TXQ_RPT_EN 0x1F
42 #define WLAN_SLOT_TIME 0x09
43 #define WLAN_RL_VAL 0x3030
44 #define WLAN_BAR_VAL 0x0201ffff
45 #define BIT_MASK_TBTT_HOLD 0x00000fff
47 #define BIT_MASK_TBTT_SETUP 0x000000ff
48 #define BIT_SHIFT_TBTT_SETUP 0
53 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
54 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
55 #define WLAN_PIFS_VAL 0
56 #define WLAN_AGG_BRK_TIME 0x16
57 #define WLAN_NAV_PROT_LEN 0x0040
58 #define WLAN_SPEC_SIFS 0x100a
59 #define WLAN_RX_PKT_LIMIT 0x17
60 #define WLAN_MAX_AGG_NR 0x0A
61 #define WLAN_AMPDU_MAX_TIME 0x1C
62 #define WLAN_ANT_SEL 0x82
63 #define WLAN_LTR_IDLE_LAT 0x90039003
64 #define WLAN_LTR_ACT_LAT 0x883c883c
65 #define WLAN_LTR_CTRL1 0xCB004010
66 #define WLAN_LTR_CTRL2 0x01233425
75 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) in rtw8723d_lck()
78 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); in rtw8723d_lck()
83 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, in rtw8723d_lck()
90 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) in rtw8723d_lck()
93 rtw_write8(rtwdev, REG_TXPAUSE, 0x00); in rtw8723d_lck()
97 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c,
98 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056,
99 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079,
100 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab,
101 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2,
102 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155,
103 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2,
104 0x7f8001fe,
108 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158,
109 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263,
110 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F,
111 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C,
112 0x7FF,
127 dm_info->delta_power_index[path] = 0; in rtw8723d_pwrtrack_init()
132 dm_info->txagc_remnant_cck = 0; in rtw8723d_pwrtrack_init()
133 dm_info->txagc_remnant_ofdm = 0; in rtw8723d_pwrtrack_init()
146 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); in rtw8723d_phy_set_param()
155 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8723d_phy_set_param()
170 rtw_write8(rtwdev, REG_ATIMWND, 0x2); in rtw8723d_phy_set_param()
195 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8723d_phy_set_param()
201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_phy_set_param()
202 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); in rtw8723d_phy_set_param()
233 efuse->rfe_option = 0; in rtw8723d_read_efuse()
237 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8723d_read_efuse()
239 efuse->country_code[0] = map->country_code[0]; in rtw8723d_read_efuse()
242 efuse->regd = map->rf_board_option & 0x7; in rtw8723d_read_efuse()
243 efuse->thermal_meter[0] = map->thermal_meter; in rtw8723d_read_efuse()
247 for (i = 0; i < 4; i++) in rtw8723d_read_efuse()
265 return 0; in rtw8723d_read_efuse()
296 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0) in query_phy_status_page1()
317 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64); in query_phy_status_page1()
318 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ in query_phy_status_page1()
327 page = *phy_status & 0xf; in query_phy_status()
330 case 0: in query_phy_status()
350 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8723d_query_rx_desc()
363 pkt_stat->ppdu_cnt = 0; in rtw8723d_query_rx_desc()
413 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); in rtw8723d_cfg_notch()
414 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8723d_cfg_notch()
415 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); in rtw8723d_cfg_notch()
416 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); in rtw8723d_cfg_notch()
417 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); in rtw8723d_cfg_notch()
418 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); in rtw8723d_cfg_notch()
419 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8723d_cfg_notch()
425 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); in rtw8723d_cfg_notch()
426 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8723d_cfg_notch()
427 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000); in rtw8723d_cfg_notch()
428 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); in rtw8723d_cfg_notch()
429 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); in rtw8723d_cfg_notch()
430 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); in rtw8723d_cfg_notch()
431 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8723d_cfg_notch()
434 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); in rtw8723d_cfg_notch()
435 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8723d_cfg_notch()
436 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); in rtw8723d_cfg_notch()
437 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); in rtw8723d_cfg_notch()
438 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); in rtw8723d_cfg_notch()
439 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000); in rtw8723d_cfg_notch()
440 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8723d_cfg_notch()
443 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8723d_cfg_notch()
444 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8723d_cfg_notch()
493 [0] = {
494 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
495 { .len = 4, .reg = 0xA28, .val = 0x00008810 },
496 { .len = 4, .reg = 0xAAC, .val = 0x01235667 },
499 { .len = 4, .reg = 0xA24, .val = 0x0000B81C },
500 { .len = 4, .reg = 0xA28, .val = 0x00000000 },
501 { .len = 4, .reg = 0xAAC, .val = 0x00003667 },
511 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; in rtw8723d_set_channel_bb()
513 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++) in rtw8723d_set_channel_bb()
518 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); in rtw8723d_set_channel_bb()
519 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); in rtw8723d_set_channel_bb()
521 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); in rtw8723d_set_channel_bb()
524 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); in rtw8723d_set_channel_bb()
525 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); in rtw8723d_set_channel_bb()
526 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); in rtw8723d_set_channel_bb()
528 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); in rtw8723d_set_channel_bb()
548 #define WLAN_RX_FILTER0 0xFFFF
549 #define WLAN_RX_FILTER1 0x400
550 #define WLAN_RX_FILTER2 0xFFFF
551 #define WLAN_RCR_CFG 0x700060CE
563 rtw_write32(rtwdev, REG_INT_MIG, 0); in rtw8723d_mac_init()
564 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); in rtw8723d_mac_init()
567 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); in rtw8723d_mac_init()
569 return 0; in rtw8723d_mac_init()
599 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8723d_set_tx_power_index_by_rate()
604 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); in rtw8723d_set_tx_power_index_by_rate()
609 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); in rtw8723d_set_tx_power_index_by_rate()
622 for (path = 0; path < hal->rf_path_num; path++) { in rtw8723d_set_tx_power_index()
623 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) in rtw8723d_set_tx_power_index()
681 dm_info->vht_err_cnt = 0; in rtw8723d_false_alarm_statistics()
682 dm_info->vht_ok_cnt = 0; in rtw8723d_false_alarm_statistics()
691 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); in rtw8723d_false_alarm_statistics()
693 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); in rtw8723d_false_alarm_statistics()
694 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); in rtw8723d_false_alarm_statistics()
695 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); in rtw8723d_false_alarm_statistics()
696 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); in rtw8723d_false_alarm_statistics()
698 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); in rtw8723d_false_alarm_statistics()
701 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); in rtw8723d_false_alarm_statistics()
705 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
706 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec
709 static const u32 iqk_mac8_regs[] = {0x522, 0x550, 0x551};
710 static const u32 iqk_mac32_regs[] = {0x40};
713 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04
742 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in rtw8723d_iqk_backup_regs()
745 for (i = 0; i < IQK_MAC8_REG_NUM; i++) in rtw8723d_iqk_backup_regs()
747 for (i = 0; i < IQK_MAC32_REG_NUM; i++) in rtw8723d_iqk_backup_regs()
750 for (i = 0; i < IQK_BB_REG_NUM; i++) in rtw8723d_iqk_backup_regs()
764 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in rtw8723d_iqk_restore_regs()
767 for (i = 0; i < IQK_MAC8_REG_NUM; i++) in rtw8723d_iqk_restore_regs()
769 for (i = 0; i < IQK_MAC32_REG_NUM; i++) in rtw8723d_iqk_restore_regs()
772 for (i = 0; i < IQK_BB_REG_NUM; i++) in rtw8723d_iqk_restore_regs()
775 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_iqk_restore_regs()
778 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); in rtw8723d_iqk_restore_regs()
781 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); in rtw8723d_iqk_restore_regs()
782 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); in rtw8723d_iqk_restore_regs()
789 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", in rtw8723d_iqk_backup_path_ctrl()
795 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); in rtw8723d_iqk_config_path_ctrl()
796 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", in rtw8723d_iqk_config_path_ctrl()
804 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", in rtw8723d_iqk_restore_path_ctrl()
812 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); in rtw8723d_iqk_backup_lte_path_gnt()
815 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", in rtw8723d_iqk_backup_lte_path_gnt()
821 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00); in rtw8723d_iqk_config_lte_path_gnt()
822 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); in rtw8723d_iqk_config_lte_path_gnt()
823 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1); in rtw8723d_iqk_config_lte_path_gnt()
830 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); in rtw8723d_iqk_restore_lte_path_gnt()
850 .val_bb_sel_btg = 0x99000000,
852 .val_txiqk_pi = 0x8214019f,
856 .val_wlint = 0xe0d,
857 .val_wlsel = 0x60d,
858 .val_iqkpts = 0xfa000000,
862 .val_bb_sel_btg = 0x99000280,
864 .val_txiqk_pi = 0x8214018a,
868 .val_wlint = 0xe6d,
869 .val_wlsel = 0x66d,
870 .val_iqkpts = 0xf9000000,
880 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", in rtw8723d_iqk_check_tx_failed()
882 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", in rtw8723d_iqk_check_tx_failed()
886 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", in rtw8723d_iqk_check_tx_failed()
887 rtw_read32(rtwdev, 0xe90), in rtw8723d_iqk_check_tx_failed()
888 rtw_read32(rtwdev, 0xe98)); in rtw8723d_iqk_check_tx_failed()
900 return 0; in rtw8723d_iqk_check_tx_failed()
909 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", in rtw8723d_iqk_check_rx_failed()
914 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", in rtw8723d_iqk_check_rx_failed()
915 rtw_read32(rtwdev, 0xea0), in rtw8723d_iqk_check_rx_failed()
916 rtw_read32(rtwdev, 0xea8)); in rtw8723d_iqk_check_rx_failed()
930 return 0; in rtw8723d_iqk_check_rx_failed()
936 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000); in rtw8723d_iqk_one_shot()
942 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054); in rtw8723d_iqk_one_shot()
944 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n", in rtw8723d_iqk_one_shot()
947 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n", in rtw8723d_iqk_one_shot()
953 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); in rtw8723d_iqk_one_shot()
970 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0); in rtw8723d_iqk_txrx_path_post()
971 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0); in rtw8723d_iqk_txrx_path_post()
972 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0); in rtw8723d_iqk_txrx_path_post()
982 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n", in rtw8723d_iqk_tx_path()
989 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); in rtw8723d_iqk_tx_path()
990 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004); in rtw8723d_iqk_tx_path()
991 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d); in rtw8723d_iqk_tx_path()
992 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0); in rtw8723d_iqk_tx_path()
993 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_tx_path()
996 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c); in rtw8723d_iqk_tx_path()
997 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); in rtw8723d_iqk_tx_path()
999 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200); in rtw8723d_iqk_tx_path()
1000 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); in rtw8723d_iqk_tx_path()
1001 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_tx_path()
1004 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); in rtw8723d_iqk_tx_path()
1007 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); in rtw8723d_iqk_tx_path()
1008 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); in rtw8723d_iqk_tx_path()
1009 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3); in rtw8723d_iqk_tx_path()
1010 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf); in rtw8723d_iqk_tx_path()
1013 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1); in rtw8723d_iqk_tx_path()
1014 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1); in rtw8723d_iqk_tx_path()
1019 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n", in rtw8723d_iqk_tx_path()
1022 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n", in rtw8723d_iqk_tx_path()
1043 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n", in rtw8723d_iqk_rx_path()
1051 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); in rtw8723d_iqk_rx_path()
1052 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_rx_path()
1055 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); in rtw8723d_iqk_rx_path()
1056 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); in rtw8723d_iqk_rx_path()
1057 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1058 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1059 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000); in rtw8723d_iqk_rx_path()
1060 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000); in rtw8723d_iqk_rx_path()
1063 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); in rtw8723d_iqk_rx_path()
1066 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); in rtw8723d_iqk_rx_path()
1067 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006); in rtw8723d_iqk_rx_path()
1068 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); in rtw8723d_iqk_rx_path()
1069 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb); in rtw8723d_iqk_rx_path()
1070 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_rx_path()
1072 /* PA/PAD=0 */ in rtw8723d_iqk_rx_path()
1073 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); in rtw8723d_iqk_rx_path()
1074 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); in rtw8723d_iqk_rx_path()
1078 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n", in rtw8723d_iqk_rx_path()
1081 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n", in rtw8723d_iqk_rx_path()
1096 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", in rtw8723d_iqk_rx_path()
1102 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n", in rtw8723d_iqk_rx_path()
1106 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_rx_path()
1107 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); in rtw8723d_iqk_rx_path()
1108 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); in rtw8723d_iqk_rx_path()
1109 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1110 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1111 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000); in rtw8723d_iqk_rx_path()
1112 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400); in rtw8723d_iqk_rx_path()
1115 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); in rtw8723d_iqk_rx_path()
1120 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1); in rtw8723d_iqk_rx_path()
1121 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007); in rtw8723d_iqk_rx_path()
1122 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); in rtw8723d_iqk_rx_path()
1123 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb); in rtw8723d_iqk_rx_path()
1124 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_rx_path()
1126 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n", in rtw8723d_iqk_rx_path()
1129 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n", in rtw8723d_iqk_rx_path()
1150 if (result[IQK_S1_TX_X] == 0) in rtw8723d_iqk_fill_s1_matrix()
1173 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", in rtw8723d_iqk_fill_s1_matrix()
1176 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); in rtw8723d_iqk_fill_s1_matrix()
1178 if (result[IQK_S1_RX_X] == 0) in rtw8723d_iqk_fill_s1_matrix()
1197 if (result[IQK_S0_TX_X] == 0) in rtw8723d_iqk_fill_s0_matrix()
1214 if (result[IQK_S0_RX_X] == 0) in rtw8723d_iqk_fill_s0_matrix()
1227 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in rtw8723d_iqk_path_adda_on()
1228 rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016); in rtw8723d_iqk_path_adda_on()
1233 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); in rtw8723d_iqk_config_mac()
1244 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000); in rtw8723d_iqk_rf_standby()
1253 u32 bitmap = 0; in rtw8723d_iqk_similarity_cmp()
1259 for (i = 0; i < IQK_NR; i++) { in rtw8723d_iqk_similarity_cmp()
1269 if (result[c1][i] + result[c1][i + 1] == 0) in rtw8723d_iqk_similarity_cmp()
1271 else if (result[c2][i] + result[c2][i + 1] == 0) in rtw8723d_iqk_similarity_cmp()
1280 if (bitmap != 0) in rtw8723d_iqk_similarity_cmp()
1283 for (i = 0; i < PATH_NR; i++) { in rtw8723d_iqk_similarity_cmp()
1295 for (i = 0; i < IQK_NR; i++) { in rtw8723d_iqk_similarity_cmp()
1315 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); in rtw8723d_iqk_precfg_path()
1316 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_precfg_path()
1336 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); in rtw8723d_iqk_one_round()
1337 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611); in rtw8723d_iqk_one_round()
1338 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); in rtw8723d_iqk_one_round()
1339 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200); in rtw8723d_iqk_one_round()
1342 for (i = 0; i < PATH_IQK_RETRY; i++) { in rtw8723d_iqk_one_round()
1355 result[t][IQK_S1_TX_X] = 0x100; in rtw8723d_iqk_one_round()
1356 result[t][IQK_S1_TX_Y] = 0x0; in rtw8723d_iqk_one_round()
1359 for (i = 0; i < PATH_IQK_RETRY; i++) { in rtw8723d_iqk_one_round()
1372 result[t][IQK_S1_RX_X] = 0x100; in rtw8723d_iqk_one_round()
1373 result[t][IQK_S1_RX_Y] = 0x0; in rtw8723d_iqk_one_round()
1376 if (s1_ok == 0x0) in rtw8723d_iqk_one_round()
1381 for (i = 0; i < PATH_IQK_RETRY; i++) { in rtw8723d_iqk_one_round()
1394 result[t][IQK_S0_TX_X] = 0x100; in rtw8723d_iqk_one_round()
1395 result[t][IQK_S0_TX_Y] = 0x0; in rtw8723d_iqk_one_round()
1398 for (i = 0; i < PATH_IQK_RETRY; i++) { in rtw8723d_iqk_one_round()
1412 result[t][IQK_S0_RX_X] = 0x100; in rtw8723d_iqk_one_round()
1413 result[t][IQK_S0_RX_Y] = 0x0; in rtw8723d_iqk_one_round()
1416 if (s0_ok == 0x0) in rtw8723d_iqk_one_round()
1437 memset(result, 0, sizeof(result)); in rtw8723d_phy_calibration()
1468 s32 reg_tmp = 0; in rtw8723d_phy_calibration()
1470 for (i = 0; i < IQK_NR; i++) in rtw8723d_phy_calibration()
1473 if (reg_tmp != 0) { in rtw8723d_phy_calibration()
1501 result[i][0], result[i][1], result[i][2], result[i][3], in rtw8723d_phy_calibration()
1506 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", in rtw8723d_phy_calibration()
1512 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", in rtw8723d_phy_calibration()
1535 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", in rtw8723d_phy_cck_pd_set()
1543 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); in rtw8723d_phy_cck_pd_set()
1544 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, in rtw8723d_phy_cck_pd_set()
1555 /* 0x790[5:0]=0x5 */ in rtw8723d_coex_cfg_init()
1556 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8723d_coex_cfg_init()
1559 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8723d_coex_cfg_init()
1575 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0); in rtw8723d_coex_cfg_gnt_debug()
1576 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); in rtw8723d_coex_cfg_gnt_debug()
1577 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0); in rtw8723d_coex_cfg_gnt_debug()
1578 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1579 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1580 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); in rtw8723d_coex_cfg_gnt_debug()
1581 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1582 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0); in rtw8723d_coex_cfg_gnt_debug()
1593 coex_rfe->ant_switch_polarity = 0; in rtw8723d_coex_cfg_rfe_type()
1602 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80); in rtw8723d_coex_cfg_rfe_type()
1604 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200); in rtw8723d_coex_cfg_rfe_type()
1607 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280); in rtw8723d_coex_cfg_rfe_type()
1609 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0); in rtw8723d_coex_cfg_rfe_type()
1613 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); in rtw8723d_coex_cfg_rfe_type()
1614 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8723d_coex_cfg_rfe_type()
1615 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8723d_coex_cfg_rfe_type()
1622 static const u8 wl_tx_power[] = {0xb2, 0x90}; in rtw8723d_coex_cfg_wl_tx_power()
1644 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101, in rtw8723d_coex_cfg_wl_rx_gain()
1645 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101, in rtw8723d_coex_cfg_wl_rx_gain()
1646 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101, in rtw8723d_coex_cfg_wl_rx_gain()
1647 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001, in rtw8723d_coex_cfg_wl_rx_gain()
1648 0xcd260001, 0xcc270001, 0x8f280001 in rtw8723d_coex_cfg_wl_rx_gain()
1652 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101, in rtw8723d_coex_cfg_wl_rx_gain()
1653 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101, in rtw8723d_coex_cfg_wl_rx_gain()
1654 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101, in rtw8723d_coex_cfg_wl_rx_gain()
1655 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101, in rtw8723d_coex_cfg_wl_rx_gain()
1656 0x44260101, 0x43270101, 0x42280101 in rtw8723d_coex_cfg_wl_rx_gain()
1666 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) in rtw8723d_coex_cfg_wl_rx_gain()
1669 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) in rtw8723d_coex_cfg_wl_rx_gain()
1700 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); in rtw8723d_pwrtrack_get_limit_ofdm()
1742 /* write new elements A, C, D, and element B is always 0 */ in rtw8723d_set_iqk_matrix_by_result()
1755 /* write new elements A, C, D, and element B is always 0 */ in rtw8723d_set_iqk_matrix_by_result()
1779 else if (ofdm_index < 0) in rtw8723d_set_iqk_matrix()
1780 ofdm_index = 0; in rtw8723d_set_iqk_matrix()
1794 0x00); in rtw8723d_set_iqk_matrix()
1810 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1811 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1812 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1835 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, in rtw8723d_pwrtrack_set_cck_pwr()
1858 else if (final_ofdm_swing_index < 0) in rtw8723d_pwrtrack_set()
1859 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0, in rtw8723d_pwrtrack_set()
1862 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); in rtw8723d_pwrtrack_set()
1867 else if (final_cck_swing_index < 0) in rtw8723d_pwrtrack_set()
1868 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0, in rtw8723d_pwrtrack_set()
1871 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); in rtw8723d_pwrtrack_set()
1890 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8723d_pwrtrack_set_xtal()
1891 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); in rtw8723d_pwrtrack_set_xtal()
1905 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8723d_phy_pwrtrack()
1908 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8723d_phy_pwrtrack()
1927 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8723d_phy_pwrtrack()
1952 if (efuse->power_track_type != 0) in rtw8723d_pwr_track()
1957 GENMASK(17, 16), 0x03); in rtw8723d_pwr_track()
1971 __le16 chksum = 0; in rtw8723d_fill_txdesc_checksum()
1975 le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM); in rtw8723d_fill_txdesc_checksum()
2019 {0xffffffff, 0xffffffff}, /* case-0 */
2020 {0x55555555, 0x55555555},
2021 {0x66555555, 0x66555555},
2022 {0xaaaaaaaa, 0xaaaaaaaa},
2023 {0x5a5a5a5a, 0x5a5a5a5a},
2024 {0xfafafafa, 0xfafafafa}, /* case-5 */
2025 {0x6a5a5555, 0xaaaaaaaa},
2026 {0x6a5a56aa, 0x6a5a56aa},
2027 {0x6a5a5a5a, 0x6a5a5a5a},
2028 {0x66555555, 0x5a5a5a5a},
2029 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2030 {0x66555555, 0x6a5a5aaa},
2031 {0x66555555, 0x5a5a5aaa},
2032 {0x66555555, 0x6aaa5aaa},
2033 {0x66555555, 0xaaaa5aaa},
2034 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2035 {0xffff55ff, 0xfafafafa},
2036 {0xffff55ff, 0x6afa5afa},
2037 {0xaaffffaa, 0xfafafafa},
2038 {0xaa5555aa, 0x5a5a5a5a},
2039 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2040 {0xaa5555aa, 0xaaaaaaaa},
2041 {0xffffffff, 0x5a5a5a5a},
2042 {0xffffffff, 0x5a5a5a5a},
2043 {0xffffffff, 0x55555555},
2044 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
2045 {0x55555555, 0x5a5a5a5a},
2046 {0x55555555, 0xaaaaaaaa},
2047 {0x55555555, 0x6a5a6a5a},
2048 {0x66556655, 0x66556655},
2049 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2050 {0xffffffff, 0x5aaa5aaa},
2051 {0x56555555, 0x5a5a5aaa},
2056 {0xffffffff, 0xffffffff}, /* case-100 */
2057 {0x55555555, 0x55555555},
2058 {0x66555555, 0x66555555},
2059 {0xaaaaaaaa, 0xaaaaaaaa},
2060 {0x5a5a5a5a, 0x5a5a5a5a},
2061 {0xfafafafa, 0xfafafafa}, /* case-105 */
2062 {0x5afa5afa, 0x5afa5afa},
2063 {0x55555555, 0xfafafafa},
2064 {0x66555555, 0xfafafafa},
2065 {0x66555555, 0x5a5a5a5a},
2066 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2067 {0x66555555, 0xaaaaaaaa},
2068 {0xffff55ff, 0xfafafafa},
2069 {0xffff55ff, 0x5afa5afa},
2070 {0xffff55ff, 0xaaaaaaaa},
2071 {0xffff55ff, 0xffff55ff}, /* case-115 */
2072 {0xaaffffaa, 0x5afa5afa},
2073 {0xaaffffaa, 0xaaaaaaaa},
2074 {0xffffffff, 0xfafafafa},
2075 {0xffffffff, 0x5afa5afa},
2076 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2077 {0x55ff55ff, 0x5afa5afa},
2078 {0x55ff55ff, 0xaaaaaaaa},
2079 {0x55ff55ff, 0x55ff55ff}
2084 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2085 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
2086 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2087 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2088 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2089 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2090 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2091 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2092 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2093 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2094 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2095 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2096 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2097 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2098 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2099 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2100 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2101 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2102 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2103 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2104 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2105 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2106 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2107 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2108 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2109 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2110 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2111 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2116 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
2117 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2118 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2119 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2120 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2121 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2122 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2123 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2124 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2125 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2126 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2127 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2128 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2129 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2130 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2131 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2132 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2133 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2134 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2135 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2136 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2137 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2143 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
2151 {0, 0, false, 7}, /* for normal */
2152 {0, 10, false, 7}, /* for WL-CPT */
2153 {1, 0, true, 4},
2160 {0, 0, false, 7}, /* for normal */
2161 {0, 10, false, 7}, /* for WL-CPT */
2162 {1, 0, true, 5},
2169 {0x0005,
2173 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
2174 {0x0086,
2178 RTW_PWR_CMD_WRITE, BIT(0), 0},
2179 {0x0086,
2184 {0x004A,
2188 RTW_PWR_CMD_WRITE, BIT(0), 0},
2189 {0x0005,
2193 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
2194 {0x0023,
2198 RTW_PWR_CMD_WRITE, BIT(4), 0},
2199 {0x0301,
2203 RTW_PWR_CMD_WRITE, 0xFF, 0},
2204 {0xFFFF,
2207 0,
2208 RTW_PWR_CMD_END, 0, 0},
2212 {0x0020,
2216 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2217 {0x0001,
2222 {0x0000,
2226 RTW_PWR_CMD_WRITE, BIT(5), 0},
2227 {0x0005,
2231 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
2232 {0x0075,
2236 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2237 {0x0006,
2242 {0x0075,
2246 RTW_PWR_CMD_WRITE, BIT(0), 0},
2247 {0x0006,
2251 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2252 {0x0005,
2256 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
2257 {0x0005,
2261 RTW_PWR_CMD_WRITE, BIT(7), 0},
2262 {0x0005,
2266 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
2267 {0x0005,
2271 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2272 {0x0005,
2276 RTW_PWR_CMD_POLLING, BIT(0), 0},
2277 {0x0010,
2282 {0x0049,
2287 {0x0063,
2292 {0x0062,
2296 RTW_PWR_CMD_WRITE, BIT(1), 0},
2297 {0x0058,
2301 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2302 {0x005A,
2307 {0x0068,
2312 {0x0069,
2317 {0x001f,
2321 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2322 {0x0077,
2326 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2327 {0x001f,
2331 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
2332 {0x0077,
2336 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
2337 {0xFFFF,
2340 0,
2341 RTW_PWR_CMD_END, 0, 0},
2351 {0x0301,
2355 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
2356 {0x0522,
2360 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
2361 {0x05F8,
2365 RTW_PWR_CMD_POLLING, 0xFF, 0},
2366 {0x05F9,
2370 RTW_PWR_CMD_POLLING, 0xFF, 0},
2371 {0x05FA,
2375 RTW_PWR_CMD_POLLING, 0xFF, 0},
2376 {0x05FB,
2380 RTW_PWR_CMD_POLLING, 0xFF, 0},
2381 {0x0002,
2385 RTW_PWR_CMD_WRITE, BIT(0), 0},
2386 {0x0002,
2390 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
2391 {0x0002,
2395 RTW_PWR_CMD_WRITE, BIT(1), 0},
2396 {0x0100,
2400 RTW_PWR_CMD_WRITE, 0xFF, 0x03},
2401 {0x0101,
2405 RTW_PWR_CMD_WRITE, BIT(1), 0},
2406 {0x0093,
2410 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2411 {0x0553,
2416 {0xFFFF,
2419 0,
2420 RTW_PWR_CMD_END, 0, 0},
2424 {0x0003,
2428 RTW_PWR_CMD_WRITE, BIT(2), 0},
2429 {0x0080,
2433 RTW_PWR_CMD_WRITE, 0xFF, 0},
2434 {0xFFFF,
2437 0,
2438 RTW_PWR_CMD_END, 0, 0},
2442 {0x0002,
2446 RTW_PWR_CMD_WRITE, BIT(0), 0},
2447 {0x0049,
2451 RTW_PWR_CMD_WRITE, BIT(1), 0},
2452 {0x0006,
2456 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2457 {0x0005,
2462 {0x0005,
2466 RTW_PWR_CMD_POLLING, BIT(1), 0},
2467 {0x0010,
2471 RTW_PWR_CMD_WRITE, BIT(6), 0},
2472 {0x0000,
2477 {0x0020,
2481 RTW_PWR_CMD_WRITE, BIT(0), 0},
2482 {0xFFFF,
2485 0,
2486 RTW_PWR_CMD_END, 0, 0},
2490 {0x0007,
2494 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
2495 {0x0005,
2500 {0x0005,
2505 {0x0005,
2510 {0x004A,
2514 RTW_PWR_CMD_WRITE, BIT(0), 1},
2515 {0x0023,
2520 {0x0086,
2524 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2525 {0x0086,
2529 RTW_PWR_CMD_POLLING, BIT(1), 0},
2530 {0xFFFF,
2533 0,
2534 RTW_PWR_CMD_END, 0, 0},
2538 {0x001D,
2542 RTW_PWR_CMD_WRITE, BIT(0), 0},
2543 {0x001D,
2547 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2548 {0x001C,
2552 RTW_PWR_CMD_WRITE, 0xFF, 0x0E},
2553 {0xFFFF,
2556 0,
2557 RTW_PWR_CMD_END, 0, 0},
2570 {12, 2, 2, 0, 1},
2571 {12, 2, 2, 0, 1},
2572 {12, 2, 2, 0, 1},
2573 {12, 2, 2, 0, 1},
2574 {12, 2, 2, 0, 1},
2612 {0x0008, 0x4a22,
2616 {0x0009, 0x1000,
2620 {0xFFFF, 0x0000,
2632 [0] = { .addr = 0xc50, .mask = 0x7f },
2633 [1] = { .addr = 0xc50, .mask = 0x7f },
2637 [0] = { .addr = 0xa0c, .mask = 0x3f00 },
2641 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0,
2642 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8},
2643 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4,
2644 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc},
2654 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl,
2659 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2664 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2669 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2674 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2679 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2684 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2689 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2694 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2699 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2700 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2704 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2705 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2722 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2723 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2724 {0, 0, RTW_REG_DOMAIN_NL},
2725 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2726 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2727 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2728 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2729 {0, 0, RTW_REG_DOMAIN_NL},
2730 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2731 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2732 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2733 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2734 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2735 {0, 0, RTW_REG_DOMAIN_NL},
2736 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2737 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2738 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2739 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2740 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2760 .max_power_index = 0x3f,
2761 .csi_buf_pg_num = 0,
2764 .dig_min = 0x20,
2767 .lps_deep_mode_supported = 0,
2768 .sys_func_en = 0xFD,
2777 .rf_sipi_addr = {0x840, 0x844},
2793 .coex_para_ver = 0x2007022f,
2794 .bt_desired_ver = 0x2f,
2816 .bt_afh_span_bw20 = 0x20,
2817 .bt_afh_span_bw40 = 0x30,