Lines Matching refs:rtlphy

38 	struct rtl_phy *rtlphy = &rtlpriv->phy;  in rtl8821ae_phy_rf6052_set_cck_txpower()  local
75 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) + in rtl8821ae_phy_rf6052_set_cck_txpower()
76 (rtlphy->mcs_txpwrlevel_origoffset[0][7] << in rtl8821ae_phy_rf6052_set_cck_txpower()
80 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) + in rtl8821ae_phy_rf6052_set_cck_txpower()
81 (rtlphy->mcs_txpwrlevel_origoffset[0][15] << in rtl8821ae_phy_rf6052_set_cck_txpower()
125 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl8821ae_phy_get_power_base() local
141 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) in rtl8821ae_phy_get_power_base()
165 struct rtl_phy *rtlphy = &rtlpriv->phy; in get_txpower_writeval_by_regulatory() local
176 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index + in get_txpower_writeval_by_regulatory()
185 if (rtlphy->pwrgroup_cnt == 1) { in get_txpower_writeval_by_regulatory()
203 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup] in get_txpower_writeval_by_regulatory()
224 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { in get_txpower_writeval_by_regulatory()
240 else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) in get_txpower_writeval_by_regulatory()
244 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) in get_txpower_writeval_by_regulatory()
258 (u8)((rtlphy->mcs_txpwrlevel_origoffset in get_txpower_writeval_by_regulatory()
284 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup] in get_txpower_writeval_by_regulatory()
383 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl8821ae_phy_rf6052_config() local
385 if (rtlphy->rf_type == RF_1T1R) in rtl8821ae_phy_rf6052_config()
386 rtlphy->num_total_rfpath = 1; in rtl8821ae_phy_rf6052_config()
388 rtlphy->num_total_rfpath = 2; in rtl8821ae_phy_rf6052_config()
396 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl8821ae_phy_rf6052_config_parafile() local
401 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { in _rtl8821ae_phy_rf6052_config_parafile()