Lines Matching refs:PWR_BASEADDR_MAC
46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
50 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
54 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
64 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
67 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
76 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
84 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
87 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
90 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
102 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
108 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
116 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
120 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
123 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
126 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
129 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
135 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
139 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
151 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
161 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
175 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
184 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
187 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
208 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
222 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
231 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
234 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
237 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
251 PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, \
255 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
258 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
274 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
280 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
283 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
286 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
289 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
295 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
298 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
304 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
321 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
324 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
327 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
330 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
333 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
336 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
339 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
342 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
345 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
348 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},