Lines Matching refs:PWR_BASEADDR_MAC
46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
49 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
52 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
55 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
75 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
77 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
84 PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
89 PWR_BASEADDR_MAC, \
94 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
130 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
155 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
159 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
166 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
169 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
176 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
184 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
187 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
191 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
195 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
199 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
203 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
207 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
210 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
213 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
216 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
219 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
223 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
233 PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
236 PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
239 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
243 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
247 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
251 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
255 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
259 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
263 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
266 PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\