Lines Matching +full:0 +full:xe94
38 u32 original_value = 0, readback_value, bitshift; in rtl8723e_phy_query_rf_reg()
70 u32 original_value = 0, bitshift; in rtl8723e_phy_set_rf_reg()
117 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl8723e_phy_bb_config_1t()
118 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); in _rtl8723e_phy_bb_config_1t()
119 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); in _rtl8723e_phy_bb_config_1t()
120 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); in _rtl8723e_phy_bb_config_1t()
121 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); in _rtl8723e_phy_bb_config_1t()
122 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
123 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
124 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
125 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
126 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
133 rtl_write_byte(rtlpriv, 0x04CA, 0x0A); in rtl8723e_phy_mac_config()
146 /* 1. 0x28[1] = 1 */ in rtl8723e_phy_bb_config()
151 /* 2. 0x29[7:0] = 0xFF */ in rtl8723e_phy_bb_config()
152 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff); in rtl8723e_phy_bb_config()
155 /* 3. 0x02[1:0] = 2b'11 */ in rtl8723e_phy_bb_config()
160 /* 4. 0x25[6] = 0 */ in rtl8723e_phy_bb_config()
164 /* 5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09. */ in rtl8723e_phy_bb_config()
168 /* 6. 0x1f[7:0] = 0x07 */ in rtl8723e_phy_bb_config()
169 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07); in rtl8723e_phy_bb_config()
201 rtlphy->pwrgroup_cnt = 0; in _rtl8723e_phy_bb8192c_config_parafile()
217 0x200)); in _rtl8723e_phy_bb8192c_config_parafile()
235 for (i = 0; i < arraylength; i = i + 2) in _rtl8723e_phy_config_mac_with_headerfile()
254 for (i = 0; i < phy_reg_arraylen; i = i + 2) { in _rtl8723e_phy_config_bb_with_headerfile()
255 if (phy_regarray_table[i] == 0xfe) in _rtl8723e_phy_config_bb_with_headerfile()
257 else if (phy_regarray_table[i] == 0xfd) in _rtl8723e_phy_config_bb_with_headerfile()
259 else if (phy_regarray_table[i] == 0xfc) in _rtl8723e_phy_config_bb_with_headerfile()
261 else if (phy_regarray_table[i] == 0xfb) in _rtl8723e_phy_config_bb_with_headerfile()
263 else if (phy_regarray_table[i] == 0xfa) in _rtl8723e_phy_config_bb_with_headerfile()
265 else if (phy_regarray_table[i] == 0xf9) in _rtl8723e_phy_config_bb_with_headerfile()
271 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", in _rtl8723e_phy_config_bb_with_headerfile()
276 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl8723e_phy_config_bb_with_headerfile()
281 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", in _rtl8723e_phy_config_bb_with_headerfile()
297 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] = in store_pwrindex_diffrate_offset()
300 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", in store_pwrindex_diffrate_offset()
303 [rtlphy->pwrgroup_cnt][0]); in store_pwrindex_diffrate_offset()
309 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", in store_pwrindex_diffrate_offset()
318 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", in store_pwrindex_diffrate_offset()
323 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { in store_pwrindex_diffrate_offset()
327 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", in store_pwrindex_diffrate_offset()
336 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", in store_pwrindex_diffrate_offset()
345 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", in store_pwrindex_diffrate_offset()
354 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", in store_pwrindex_diffrate_offset()
363 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", in store_pwrindex_diffrate_offset()
372 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", in store_pwrindex_diffrate_offset()
381 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", in store_pwrindex_diffrate_offset()
390 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", in store_pwrindex_diffrate_offset()
395 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { in store_pwrindex_diffrate_offset()
399 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", in store_pwrindex_diffrate_offset()
408 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", in store_pwrindex_diffrate_offset()
417 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", in store_pwrindex_diffrate_offset()
426 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", in store_pwrindex_diffrate_offset()
435 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", in store_pwrindex_diffrate_offset()
456 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { in _rtl8723e_phy_config_bb_with_pgheaderfile()
457 if (phy_regarray_table_pg[i] == 0xfe) in _rtl8723e_phy_config_bb_with_pgheaderfile()
459 else if (phy_regarray_table_pg[i] == 0xfd) in _rtl8723e_phy_config_bb_with_pgheaderfile()
461 else if (phy_regarray_table_pg[i] == 0xfc) in _rtl8723e_phy_config_bb_with_pgheaderfile()
463 else if (phy_regarray_table_pg[i] == 0xfb) in _rtl8723e_phy_config_bb_with_pgheaderfile()
465 else if (phy_regarray_table_pg[i] == 0xfa) in _rtl8723e_phy_config_bb_with_pgheaderfile()
467 else if (phy_regarray_table_pg[i] == 0xf9) in _rtl8723e_phy_config_bb_with_pgheaderfile()
494 for (i = 0; i < radioa_arraylen; i = i + 2) { in rtl8723e_phy_config_rf_with_headerfile()
495 if (radioa_array_table[i] == 0xfe) { in rtl8723e_phy_config_rf_with_headerfile()
497 } else if (radioa_array_table[i] == 0xfd) { in rtl8723e_phy_config_rf_with_headerfile()
499 } else if (radioa_array_table[i] == 0xfc) { in rtl8723e_phy_config_rf_with_headerfile()
501 } else if (radioa_array_table[i] == 0xfb) { in rtl8723e_phy_config_rf_with_headerfile()
503 } else if (radioa_array_table[i] == 0xfa) { in rtl8723e_phy_config_rf_with_headerfile()
505 } else if (radioa_array_table[i] == 0xf9) { in rtl8723e_phy_config_rf_with_headerfile()
528 rtlphy->default_initialgain[0] = in rtl8723e_phy_get_hw_reg_originalvalue()
538 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl8723e_phy_get_hw_reg_originalvalue()
539 rtlphy->default_initialgain[0], in rtl8723e_phy_get_hw_reg_originalvalue()
550 "Default framesync (0x%x) = 0x%x\n", in rtl8723e_phy_get_hw_reg_originalvalue()
615 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl8723e_ccxpower_index_check()
616 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl8723e_ccxpower_index_check()
628 &cckpowerlevel[0], &ofdmpowerlevel[0]); in rtl8723e_phy_set_txpower_level()
630 channel, &cckpowerlevel[0], in rtl8723e_phy_set_txpower_level()
631 &ofdmpowerlevel[0]); in rtl8723e_phy_set_txpower_level()
632 rtl8723e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl8723e_phy_set_txpower_level()
633 rtl8723e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); in rtl8723e_phy_set_txpower_level()
649 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0) in rtl8723e_phy_update_txpower_dbm()
652 ofdmtxpwridx = 0; in rtl8723e_phy_update_txpower_dbm()
656 for (idx = 0; idx < 14; idx++) { in rtl8723e_phy_update_txpower_dbm()
657 for (rf_path = 0; rf_path < 2; rf_path++) { in rtl8723e_phy_update_txpower_dbm()
689 if ((power_indbm - offset) > 0) in _rtl8723e_phy_dbm_to_txpwr_idx()
692 txpwridx = 0; in _rtl8723e_phy_dbm_to_txpwr_idx()
759 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); in rtl8723e_phy_set_bw_mode_callback()
770 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl8723e_phy_set_bw_mode_callback()
771 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl8723e_phy_set_bw_mode_callback()
775 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl8723e_phy_set_bw_mode_callback()
776 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl8723e_phy_set_bw_mode_callback()
780 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl8723e_phy_set_bw_mode_callback()
781 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); in rtl8723e_phy_set_bw_mode_callback()
783 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl8723e_phy_set_bw_mode_callback()
835 if (delay > 0) in rtl8723e_phy_sw_chnl_callback()
854 return 0; in rtl8723e_phy_sw_chnl()
856 return 0; in rtl8723e_phy_sw_chnl()
860 rtlphy->sw_chnl_stage = 0; in rtl8723e_phy_sw_chnl()
861 rtlphy->sw_chnl_step = 0; in rtl8723e_phy_sw_chnl()
885 MASKDWORD, 0x00255); in _rtl8723e_phy_sw_rf_seting()
912 precommoncmdcnt = 0; in _rtl8723e_phy_sw_chnl_step_by_step()
915 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl8723e_phy_sw_chnl_step_by_step()
917 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl8723e_phy_sw_chnl_step_by_step()
919 postcommoncmdcnt = 0; in _rtl8723e_phy_sw_chnl_step_by_step()
922 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl8723e_phy_sw_chnl_step_by_step()
924 rfdependcmdcnt = 0; in _rtl8723e_phy_sw_chnl_step_by_step()
934 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, in _rtl8723e_phy_sw_chnl_step_by_step()
935 0); in _rtl8723e_phy_sw_chnl_step_by_step()
939 case 0: in _rtl8723e_phy_sw_chnl_step_by_step()
959 (*step) = 0; in _rtl8723e_phy_sw_chnl_step_by_step()
981 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl8723e_phy_sw_chnl_step_by_step()
984 0xfffffc00) | currentcmd->para2); in _rtl8723e_phy_sw_chnl_step_by_step()
1011 u8 result = 0x00; in _rtl8723e_phy_path_a_iqk()
1013 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl8723e_phy_path_a_iqk()
1014 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl8723e_phy_path_a_iqk()
1015 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl8723e_phy_path_a_iqk()
1016 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, in _rtl8723e_phy_path_a_iqk()
1017 config_pathb ? 0x28160202 : 0x28160502); in _rtl8723e_phy_path_a_iqk()
1020 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl8723e_phy_path_a_iqk()
1021 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl8723e_phy_path_a_iqk()
1022 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl8723e_phy_path_a_iqk()
1023 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); in _rtl8723e_phy_path_a_iqk()
1026 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); in _rtl8723e_phy_path_a_iqk()
1027 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl8723e_phy_path_a_iqk()
1028 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl8723e_phy_path_a_iqk()
1032 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl8723e_phy_path_a_iqk()
1033 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl8723e_phy_path_a_iqk()
1034 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl8723e_phy_path_a_iqk()
1035 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl8723e_phy_path_a_iqk()
1038 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl8723e_phy_path_a_iqk()
1039 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl8723e_phy_path_a_iqk()
1040 result |= 0x01; in _rtl8723e_phy_path_a_iqk()
1045 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl8723e_phy_path_a_iqk()
1046 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl8723e_phy_path_a_iqk()
1047 result |= 0x02; in _rtl8723e_phy_path_a_iqk()
1054 u8 result = 0x00; in _rtl8723e_phy_path_b_iqk()
1056 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl8723e_phy_path_b_iqk()
1057 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl8723e_phy_path_b_iqk()
1059 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl8723e_phy_path_b_iqk()
1060 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl8723e_phy_path_b_iqk()
1061 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl8723e_phy_path_b_iqk()
1062 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl8723e_phy_path_b_iqk()
1063 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl8723e_phy_path_b_iqk()
1066 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl8723e_phy_path_b_iqk()
1067 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) in _rtl8723e_phy_path_b_iqk()
1068 result |= 0x01; in _rtl8723e_phy_path_b_iqk()
1072 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl8723e_phy_path_b_iqk()
1073 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) in _rtl8723e_phy_path_b_iqk()
1074 result |= 0x02; in _rtl8723e_phy_path_b_iqk()
1083 u8 final_candidate[2] = { 0xFF, 0xFF }; in _rtl8723e_phy_simularity_compare()
1088 simularity_bitmap = 0; in _rtl8723e_phy_simularity_compare()
1090 for (i = 0; i < bound; i++) { in _rtl8723e_phy_simularity_compare()
1097 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl8723e_phy_simularity_compare()
1099 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl8723e_phy_simularity_compare()
1110 if (simularity_bitmap == 0) { in _rtl8723e_phy_simularity_compare()
1111 for (i = 0; i < (bound / 4); i++) { in _rtl8723e_phy_simularity_compare()
1112 if (final_candidate[i] != 0xFF) { in _rtl8723e_phy_simularity_compare()
1120 } else if (!(simularity_bitmap & 0x0F)) { in _rtl8723e_phy_simularity_compare()
1121 for (i = 0; i < 4; i++) in _rtl8723e_phy_simularity_compare()
1138 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl8723e_phy_iq_calibrate()
1139 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl8723e_phy_iq_calibrate()
1140 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl8723e_phy_iq_calibrate()
1141 0xed8, 0xedc, 0xee0, 0xeec in _rtl8723e_phy_iq_calibrate()
1145 0x522, 0x550, 0x551, 0x040 in _rtl8723e_phy_iq_calibrate()
1150 if (t == 0) { in _rtl8723e_phy_iq_calibrate()
1151 rtl_get_bbreg(hw, 0x800, MASKDWORD); in _rtl8723e_phy_iq_calibrate()
1159 if (t == 0) { in _rtl8723e_phy_iq_calibrate()
1167 if (t == 0) { in _rtl8723e_phy_iq_calibrate()
1168 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); in _rtl8723e_phy_iq_calibrate()
1169 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); in _rtl8723e_phy_iq_calibrate()
1170 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); in _rtl8723e_phy_iq_calibrate()
1172 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl8723e_phy_iq_calibrate()
1173 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl8723e_phy_iq_calibrate()
1174 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl8723e_phy_iq_calibrate()
1176 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl8723e_phy_iq_calibrate()
1177 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); in _rtl8723e_phy_iq_calibrate()
1181 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); in _rtl8723e_phy_iq_calibrate()
1183 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); in _rtl8723e_phy_iq_calibrate()
1184 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl8723e_phy_iq_calibrate()
1185 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl8723e_phy_iq_calibrate()
1186 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl8723e_phy_iq_calibrate()
1187 for (i = 0; i < retrycount; i++) { in _rtl8723e_phy_iq_calibrate()
1189 if (patha_ok == 0x03) { in _rtl8723e_phy_iq_calibrate()
1190 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1191 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1192 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1193 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1194 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1195 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1196 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1197 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1199 } else if (i == (retrycount - 1) && patha_ok == 0x01) in _rtl8723e_phy_iq_calibrate()
1201 result[t][0] = (rtl_get_bbreg(hw, 0xe94, in _rtl8723e_phy_iq_calibrate()
1202 MASKDWORD) & 0x3FF0000) >> in _rtl8723e_phy_iq_calibrate()
1205 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1212 for (i = 0; i < retrycount; i++) { in _rtl8723e_phy_iq_calibrate()
1214 if (pathb_ok == 0x03) { in _rtl8723e_phy_iq_calibrate()
1216 0xeb4, in _rtl8723e_phy_iq_calibrate()
1218 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1220 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1221 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1223 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1224 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1226 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1227 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1229 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl8723e_phy_iq_calibrate()
1231 0xeb4, in _rtl8723e_phy_iq_calibrate()
1233 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1235 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl8723e_phy_iq_calibrate()
1236 0x3FF0000) >> 16; in _rtl8723e_phy_iq_calibrate()
1239 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); in _rtl8723e_phy_iq_calibrate()
1240 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); in _rtl8723e_phy_iq_calibrate()
1241 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); in _rtl8723e_phy_iq_calibrate()
1242 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl8723e_phy_iq_calibrate()
1243 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); in _rtl8723e_phy_iq_calibrate()
1245 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); in _rtl8723e_phy_iq_calibrate()
1246 if (t != 0) { in _rtl8723e_phy_iq_calibrate()
1259 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; in _rtl8723e_phy_lc_calibrate()
1262 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl8723e_phy_lc_calibrate()
1264 if ((tmpreg & 0x70) != 0) in _rtl8723e_phy_lc_calibrate()
1265 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl8723e_phy_lc_calibrate()
1267 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl8723e_phy_lc_calibrate()
1269 if ((tmpreg & 0x70) != 0) { in _rtl8723e_phy_lc_calibrate()
1270 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl8723e_phy_lc_calibrate()
1273 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, in _rtl8723e_phy_lc_calibrate()
1276 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl8723e_phy_lc_calibrate()
1277 (rf_a_mode & 0x8FFFF) | 0x10000); in _rtl8723e_phy_lc_calibrate()
1280 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl8723e_phy_lc_calibrate()
1281 (rf_b_mode & 0x8FFFF) | 0x10000); in _rtl8723e_phy_lc_calibrate()
1283 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl8723e_phy_lc_calibrate()
1285 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl8723e_phy_lc_calibrate()
1289 if ((tmpreg & 0x70) != 0) { in _rtl8723e_phy_lc_calibrate()
1290 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl8723e_phy_lc_calibrate()
1291 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl8723e_phy_lc_calibrate()
1294 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl8723e_phy_lc_calibrate()
1297 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl8723e_phy_lc_calibrate()
1307 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); in _rtl8723e_phy_set_rfpath_switch()
1308 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl8723e_phy_set_rfpath_switch()
1313 BIT(5) | BIT(6), 0x1); in _rtl8723e_phy_set_rfpath_switch()
1316 BIT(5) | BIT(6), 0x2); in _rtl8723e_phy_set_rfpath_switch()
1319 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); in _rtl8723e_phy_set_rfpath_switch()
1321 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); in _rtl8723e_phy_set_rfpath_switch()
1339 reg_tmp = 0; in rtl8723e_phy_iq_calibrate()
1360 for (i = 0; i < 8; i++) { in rtl8723e_phy_iq_calibrate()
1361 result[0][i] = 0; in rtl8723e_phy_iq_calibrate()
1362 result[1][i] = 0; in rtl8723e_phy_iq_calibrate()
1363 result[2][i] = 0; in rtl8723e_phy_iq_calibrate()
1364 result[3][i] = 0; in rtl8723e_phy_iq_calibrate()
1366 final_candidate = 0xff; in rtl8723e_phy_iq_calibrate()
1371 for (i = 0; i < 3; i++) { in rtl8723e_phy_iq_calibrate()
1375 _rtl8723e_phy_simularity_compare(hw, result, 0, 1); in rtl8723e_phy_iq_calibrate()
1377 final_candidate = 0; in rtl8723e_phy_iq_calibrate()
1383 _rtl8723e_phy_simularity_compare(hw, result, 0, 2); in rtl8723e_phy_iq_calibrate()
1385 final_candidate = 0; in rtl8723e_phy_iq_calibrate()
1393 for (i = 0; i < 8; i++) in rtl8723e_phy_iq_calibrate()
1396 if (reg_tmp != 0) in rtl8723e_phy_iq_calibrate()
1399 final_candidate = 0xFF; in rtl8723e_phy_iq_calibrate()
1403 for (i = 0; i < 4; i++) { in rtl8723e_phy_iq_calibrate()
1404 reg_e94 = result[i][0]; in rtl8723e_phy_iq_calibrate()
1410 if (final_candidate != 0xff) { in rtl8723e_phy_iq_calibrate()
1411 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; in rtl8723e_phy_iq_calibrate()
1418 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; in rtl8723e_phy_iq_calibrate()
1419 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; in rtl8723e_phy_iq_calibrate()
1421 if (reg_e94 != 0) in rtl8723e_phy_iq_calibrate()
1424 (reg_ea4 == 0)); in rtl8723e_phy_iq_calibrate()
1494 dm_digtable->cur_igvalue = 0x17; in rtl8723e_phy_set_io()
1512 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl8723e_phy_set_rf_on()
1513 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl8723e_phy_set_rf_on()
1514 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in rtl8723e_phy_set_rf_on()
1515 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl8723e_phy_set_rf_on()
1516 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl8723e_phy_set_rf_on()
1517 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl8723e_phy_set_rf_on()
1526 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl8723e_phy_set_rf_sleep()
1527 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl8723e_phy_set_rf_sleep()
1528 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl8723e_phy_set_rf_sleep()
1529 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl8723e_phy_set_rf_sleep()
1530 while (u4b_tmp != 0 && delay > 0) { in _rtl8723e_phy_set_rf_sleep()
1531 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl8723e_phy_set_rf_sleep()
1532 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl8723e_phy_set_rf_sleep()
1533 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl8723e_phy_set_rf_sleep()
1534 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl8723e_phy_set_rf_sleep()
1537 if (delay == 0) { in _rtl8723e_phy_set_rf_sleep()
1538 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl8723e_phy_set_rf_sleep()
1539 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl8723e_phy_set_rf_sleep()
1540 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl8723e_phy_set_rf_sleep()
1541 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl8723e_phy_set_rf_sleep()
1546 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl8723e_phy_set_rf_sleep()
1547 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl8723e_phy_set_rf_sleep()
1566 u32 initializecount = 0; in _rtl8723e_phy_set_rf_power_state()
1611 for (queue_id = 0, i = 0; in _rtl8723e_phy_set_rf_power_state()
1615 skb_queue_len(&ring->queue) == 0) { in _rtl8723e_phy_set_rf_power_state()