Lines Matching refs:rtlphy
65 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_rf_serial_read() local
66 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92s_phy_rf_serial_read()
123 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_rf_serial_write() local
124 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92s_phy_rf_serial_write()
169 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92s_phy_set_rf_reg() local
172 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1)) in rtl92s_phy_set_rf_reg()
223 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92s_phy_set_bw_mode() local
228 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? in rtl92s_phy_set_bw_mode()
231 if (rtlphy->set_bwmode_inprogress) in rtl92s_phy_set_bw_mode()
236 rtlphy->set_bwmode_inprogress = true; in rtl92s_phy_set_bw_mode()
242 switch (rtlphy->current_chan_bw) { in rtl92s_phy_set_bw_mode()
253 rtlphy->current_chan_bw); in rtl92s_phy_set_bw_mode()
257 switch (rtlphy->current_chan_bw) { in rtl92s_phy_set_bw_mode()
278 rtlphy->current_chan_bw); in rtl92s_phy_set_bw_mode()
282 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); in rtl92s_phy_set_bw_mode()
283 rtlphy->set_bwmode_inprogress = false; in rtl92s_phy_set_bw_mode()
314 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_sw_chnl_step_by_step() local
323 u8 num_total_rfpath = rtlphy->num_total_rfpath; in _rtl92s_phy_sw_chnl_step_by_step()
391 rtlphy->rfreg_chnlval[rfpath] = in _rtl92s_phy_sw_chnl_step_by_step()
392 ((rtlphy->rfreg_chnlval[rfpath] & in _rtl92s_phy_sw_chnl_step_by_step()
397 rtlphy->rfreg_chnlval[rfpath]); in _rtl92s_phy_sw_chnl_step_by_step()
418 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92s_phy_sw_chnl() local
423 rtlphy->current_channel); in rtl92s_phy_sw_chnl()
425 if (rtlphy->sw_chnl_inprogress) in rtl92s_phy_sw_chnl()
428 if (rtlphy->set_bwmode_inprogress) in rtl92s_phy_sw_chnl()
434 rtlphy->sw_chnl_inprogress = true; in rtl92s_phy_sw_chnl()
435 rtlphy->sw_chnl_stage = 0; in rtl92s_phy_sw_chnl()
436 rtlphy->sw_chnl_step = 0; in rtl92s_phy_sw_chnl()
439 if (!rtlphy->sw_chnl_inprogress) in rtl92s_phy_sw_chnl()
443 rtlphy->current_channel, in rtl92s_phy_sw_chnl()
444 &rtlphy->sw_chnl_stage, in rtl92s_phy_sw_chnl()
445 &rtlphy->sw_chnl_step, &delay); in rtl92s_phy_sw_chnl()
452 rtlphy->sw_chnl_inprogress = false; in rtl92s_phy_sw_chnl()
457 rtlphy->sw_chnl_inprogress = false; in rtl92s_phy_sw_chnl()
638 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_store_pwrindex_diffrate_offset() local
658 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; in _rtl92s_store_pwrindex_diffrate_offset()
660 rtlphy->pwrgroup_cnt++; in _rtl92s_store_pwrindex_diffrate_offset()
666 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_init_register_definition() local
669 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92s_phy_init_register_definition()
670 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92s_phy_init_register_definition()
671 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92s_phy_init_register_definition()
672 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92s_phy_init_register_definition()
675 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92s_phy_init_register_definition()
676 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92s_phy_init_register_definition()
677 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92s_phy_init_register_definition()
678 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92s_phy_init_register_definition()
681 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
682 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
683 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
684 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
687 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
688 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
689 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
690 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()
693 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = in _rtl92s_phy_init_register_definition()
695 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = in _rtl92s_phy_init_register_definition()
697 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset = in _rtl92s_phy_init_register_definition()
699 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset = in _rtl92s_phy_init_register_definition()
703 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92s_phy_init_register_definition()
704 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl92s_phy_init_register_definition()
705 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92s_phy_init_register_definition()
706 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92s_phy_init_register_definition()
709 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()
710 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()
711 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()
712 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()
715 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; in _rtl92s_phy_init_register_definition()
716 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; in _rtl92s_phy_init_register_definition()
717 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1; in _rtl92s_phy_init_register_definition()
718 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1; in _rtl92s_phy_init_register_definition()
721 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; in _rtl92s_phy_init_register_definition()
722 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; in _rtl92s_phy_init_register_definition()
723 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2; in _rtl92s_phy_init_register_definition()
724 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2; in _rtl92s_phy_init_register_definition()
727 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92s_phy_init_register_definition()
728 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92s_phy_init_register_definition()
729 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92s_phy_init_register_definition()
730 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92s_phy_init_register_definition()
733 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; in _rtl92s_phy_init_register_definition()
734 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; in _rtl92s_phy_init_register_definition()
735 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; in _rtl92s_phy_init_register_definition()
736 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl92s_phy_init_register_definition()
739 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; in _rtl92s_phy_init_register_definition()
740 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; in _rtl92s_phy_init_register_definition()
741 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; in _rtl92s_phy_init_register_definition()
742 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl92s_phy_init_register_definition()
745 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
746 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
747 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
748 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
751 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; in _rtl92s_phy_init_register_definition()
752 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; in _rtl92s_phy_init_register_definition()
753 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; in _rtl92s_phy_init_register_definition()
754 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl92s_phy_init_register_definition()
757 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
758 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
759 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
760 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; in _rtl92s_phy_init_register_definition()
763 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; in _rtl92s_phy_init_register_definition()
764 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; in _rtl92s_phy_init_register_definition()
765 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; in _rtl92s_phy_init_register_definition()
766 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; in _rtl92s_phy_init_register_definition()
769 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; in _rtl92s_phy_init_register_definition()
770 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; in _rtl92s_phy_init_register_definition()
771 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; in _rtl92s_phy_init_register_definition()
772 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; in _rtl92s_phy_init_register_definition()
775 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; in _rtl92s_phy_init_register_definition()
776 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; in _rtl92s_phy_init_register_definition()
820 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_set_bb_to_diff_rf() local
825 if (rtlphy->rf_type == RF_1T1R) { in _rtl92s_phy_set_bb_to_diff_rf()
828 } else if (rtlphy->rf_type == RF_1T2R) { in _rtl92s_phy_set_bb_to_diff_rf()
878 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_bb_config_parafile() local
884 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R || in _rtl92s_phy_bb_config_parafile()
885 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) { in _rtl92s_phy_bb_config_parafile()
888 if (rtlphy->rf_type != RF_2T2R && in _rtl92s_phy_bb_config_parafile()
889 rtlphy->rf_type != RF_2T2R_GREEN) in _rtl92s_phy_bb_config_parafile()
906 rtlphy->pwrgroup_cnt = 0; in _rtl92s_phy_bb_config_parafile()
926 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw, in _rtl92s_phy_bb_config_parafile()
936 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92s_phy_config_rf() local
947 if (rtlphy->rf_type == RF_2T2R_GREEN) { in rtl92s_phy_config_rf()
1009 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92s_phy_bb_config() local
1027 rtlphy->rf_pathmap = pathmap; in rtl92s_phy_bb_config()
1033 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) || in rtl92s_phy_bb_config()
1034 (rtlphy->rf_type == RF_1T2R && rf_num != 2) || in rtl92s_phy_bb_config()
1035 (rtlphy->rf_type == RF_2T2R && rf_num != 2) || in rtl92s_phy_bb_config()
1036 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) { in rtl92s_phy_bb_config()
1038 rtlphy->rf_type, rf_num); in rtl92s_phy_bb_config()
1049 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92s_phy_rf_config() local
1052 if (rtlphy->rf_type == RF_1T1R) in rtl92s_phy_rf_config()
1053 rtlphy->num_total_rfpath = 1; in rtl92s_phy_rf_config()
1055 rtlphy->num_total_rfpath = 2; in rtl92s_phy_rf_config()
1064 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92s_phy_get_hw_reg_originalvalue() local
1067 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, in rtl92s_phy_get_hw_reg_originalvalue()
1069 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, in rtl92s_phy_get_hw_reg_originalvalue()
1071 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, in rtl92s_phy_get_hw_reg_originalvalue()
1073 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, in rtl92s_phy_get_hw_reg_originalvalue()
1077 rtlphy->default_initialgain[0], in rtl92s_phy_get_hw_reg_originalvalue()
1078 rtlphy->default_initialgain[1], in rtl92s_phy_get_hw_reg_originalvalue()
1079 rtlphy->default_initialgain[2], in rtl92s_phy_get_hw_reg_originalvalue()
1080 rtlphy->default_initialgain[3]); in rtl92s_phy_get_hw_reg_originalvalue()
1083 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0); in rtl92s_phy_get_hw_reg_originalvalue()
1084 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, in rtl92s_phy_get_hw_reg_originalvalue()
1088 ROFDM0_RXDETECTOR3, rtlphy->framesync); in rtl92s_phy_get_hw_reg_originalvalue()
1096 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_get_txpower_index() local
1107 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { in _rtl92s_phy_get_txpower_index()
1111 } else if (rtlphy->rf_type == RF_2T2R) { in _rtl92s_phy_get_txpower_index()
1125 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_ccxpower_indexcheck() local
1127 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92s_phy_ccxpower_indexcheck()
1128 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92s_phy_ccxpower_indexcheck()
1187 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92s_phy_set_fwcmd_io() local
1265 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); in _rtl92s_phy_set_fwcmd_io()