Lines Matching refs:rtlphy
138 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_rf_serial_read() local
139 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92ee_phy_rf_serial_read()
187 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_rf_serial_write() local
188 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92ee_phy_rf_serial_write()
370 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_init_tx_power_by_rate() local
378 rtlphy->tx_power_by_rate_offset in _rtl92ee_phy_init_tx_power_by_rate()
388 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_set_txpower_by_rate_base() local
399 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value; in _rtl92ee_phy_set_txpower_by_rate_base()
402 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value; in _rtl92ee_phy_set_txpower_by_rate_base()
405 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value; in _rtl92ee_phy_set_txpower_by_rate_base()
408 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value; in _rtl92ee_phy_set_txpower_by_rate_base()
427 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_get_txpower_by_rate_base() local
439 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0]; in _rtl92ee_phy_get_txpower_by_rate_base()
442 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1]; in _rtl92ee_phy_get_txpower_by_rate_base()
445 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2]; in _rtl92ee_phy_get_txpower_by_rate_base()
448 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3]; in _rtl92ee_phy_get_txpower_by_rate_base()
466 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_store_txpower_by_rate_base() local
472 raw = (u16)(rtlphy->tx_power_by_rate_offset in _rtl92ee_phy_store_txpower_by_rate_base()
480 raw = (u16)(rtlphy->tx_power_by_rate_offset in _rtl92ee_phy_store_txpower_by_rate_base()
488 raw = (u16)(rtlphy->tx_power_by_rate_offset in _rtl92ee_phy_store_txpower_by_rate_base()
494 raw = (u16)(rtlphy->tx_power_by_rate_offset in _rtl92ee_phy_store_txpower_by_rate_base()
501 raw = (u16)(rtlphy->tx_power_by_rate_offset in _rtl92ee_phy_store_txpower_by_rate_base()
537 struct rtl_phy *rtlphy = &rtlpriv->phy; in phy_convert_txpwr_dbm_to_rel_val() local
546 &rtlphy->tx_power_by_rate_offset in phy_convert_txpwr_dbm_to_rel_val()
550 &rtlphy->tx_power_by_rate_offset in phy_convert_txpwr_dbm_to_rel_val()
558 &rtlphy->tx_power_by_rate_offset in phy_convert_txpwr_dbm_to_rel_val()
562 &rtlphy->tx_power_by_rate_offset in phy_convert_txpwr_dbm_to_rel_val()
569 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0], in phy_convert_txpwr_dbm_to_rel_val()
572 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][1], in phy_convert_txpwr_dbm_to_rel_val()
579 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][4], in phy_convert_txpwr_dbm_to_rel_val()
582 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][5], in phy_convert_txpwr_dbm_to_rel_val()
589 &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][6], in phy_convert_txpwr_dbm_to_rel_val()
593 &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][7], in phy_convert_txpwr_dbm_to_rel_val()
610 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_bb8192ee_config_parafile() local
622 rtlphy->pwrgroup_cnt = 0; in _rtl92ee_phy_bb8192ee_config_parafile()
636 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, in _rtl92ee_phy_bb8192ee_config_parafile()
830 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_store_tx_power_by_rate() local
848 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][section] = data; in _rtl92ee_store_tx_power_by_rate()
1005 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_get_hw_reg_originalvalue() local
1007 rtlphy->default_initialgain[0] = in rtl92ee_phy_get_hw_reg_originalvalue()
1009 rtlphy->default_initialgain[1] = in rtl92ee_phy_get_hw_reg_originalvalue()
1011 rtlphy->default_initialgain[2] = in rtl92ee_phy_get_hw_reg_originalvalue()
1013 rtlphy->default_initialgain[3] = in rtl92ee_phy_get_hw_reg_originalvalue()
1018 rtlphy->default_initialgain[0], in rtl92ee_phy_get_hw_reg_originalvalue()
1019 rtlphy->default_initialgain[1], in rtl92ee_phy_get_hw_reg_originalvalue()
1020 rtlphy->default_initialgain[2], in rtl92ee_phy_get_hw_reg_originalvalue()
1021 rtlphy->default_initialgain[3]); in rtl92ee_phy_get_hw_reg_originalvalue()
1023 rtlphy->framesync = (u8)rtl_get_bbreg(hw, in rtl92ee_phy_get_hw_reg_originalvalue()
1025 rtlphy->framesync_c34 = rtl_get_bbreg(hw, in rtl92ee_phy_get_hw_reg_originalvalue()
1030 ROFDM0_RXDETECTOR3, rtlphy->framesync); in rtl92ee_phy_get_hw_reg_originalvalue()
1036 struct rtl_phy *rtlphy = &rtlpriv->phy; in phy_init_bb_rf_register_def() local
1038 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; in phy_init_bb_rf_register_def()
1039 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; in phy_init_bb_rf_register_def()
1041 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; in phy_init_bb_rf_register_def()
1042 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; in phy_init_bb_rf_register_def()
1044 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; in phy_init_bb_rf_register_def()
1045 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; in phy_init_bb_rf_register_def()
1047 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = in phy_init_bb_rf_register_def()
1049 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = in phy_init_bb_rf_register_def()
1052 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; in phy_init_bb_rf_register_def()
1053 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; in phy_init_bb_rf_register_def()
1055 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; in phy_init_bb_rf_register_def()
1056 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; in phy_init_bb_rf_register_def()
1058 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; in phy_init_bb_rf_register_def()
1059 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; in phy_init_bb_rf_register_def()
1065 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_get_txpower_level() local
1069 txpwr_level = rtlphy->cur_cck_txpwridx; in rtl92ee_phy_get_txpower_level()
1072 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; in rtl92ee_phy_get_txpower_level()
1077 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; in rtl92ee_phy_get_txpower_level()
1153 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_get_txpower_by_rate() local
1209 diff = (u8)(rtlphy->tx_power_by_rate_offset[band][rf][tx_num][sec] >> in _rtl92ee_get_txpower_by_rate()
1535 struct rtl_phy *rtlphy = &rtlpriv->phy; in phy_set_txpower_index_by_rate_section() local
1542 rtlphy->current_chan_bw, in phy_set_txpower_index_by_rate_section()
1550 rtlphy->current_chan_bw, in phy_set_txpower_index_by_rate_section()
1558 rtlphy->current_chan_bw, in phy_set_txpower_index_by_rate_section()
1566 rtlphy->current_chan_bw, in phy_set_txpower_index_by_rate_section()
1576 struct rtl_phy *rtlphy = &rtl_priv(hw)->phy; in rtl92ee_phy_set_txpower_level() local
1581 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; in rtl92ee_phy_set_txpower_level()
1591 if (rtlphy->num_total_rfpath >= 2) in rtl92ee_phy_set_txpower_level()
1651 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_set_bw_mode_callback() local
1658 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? in rtl92ee_phy_set_bw_mode_callback()
1662 rtlphy->set_bwmode_inprogress = false; in rtl92ee_phy_set_bw_mode_callback()
1669 switch (rtlphy->current_chan_bw) { in rtl92ee_phy_set_bw_mode_callback()
1683 rtlphy->current_chan_bw); in rtl92ee_phy_set_bw_mode_callback()
1687 switch (rtlphy->current_chan_bw) { in rtl92ee_phy_set_bw_mode_callback()
1708 rtlphy->current_chan_bw); in rtl92ee_phy_set_bw_mode_callback()
1711 rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); in rtl92ee_phy_set_bw_mode_callback()
1712 rtlphy->set_bwmode_inprogress = false; in rtl92ee_phy_set_bw_mode_callback()
1720 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_set_bw_mode() local
1722 u8 tmp_bw = rtlphy->current_chan_bw; in rtl92ee_phy_set_bw_mode()
1724 if (rtlphy->set_bwmode_inprogress) in rtl92ee_phy_set_bw_mode()
1726 rtlphy->set_bwmode_inprogress = true; in rtl92ee_phy_set_bw_mode()
1732 rtlphy->set_bwmode_inprogress = false; in rtl92ee_phy_set_bw_mode()
1733 rtlphy->current_chan_bw = tmp_bw; in rtl92ee_phy_set_bw_mode()
1741 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_sw_chnl_callback() local
1745 "switch to channel%d\n", rtlphy->current_channel); in rtl92ee_phy_sw_chnl_callback()
1749 if (!rtlphy->sw_chnl_inprogress) in rtl92ee_phy_sw_chnl_callback()
1752 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, in rtl92ee_phy_sw_chnl_callback()
1753 &rtlphy->sw_chnl_step, &delay)) { in rtl92ee_phy_sw_chnl_callback()
1759 rtlphy->sw_chnl_inprogress = false; in rtl92ee_phy_sw_chnl_callback()
1769 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_sw_chnl() local
1772 if (rtlphy->sw_chnl_inprogress) in rtl92ee_phy_sw_chnl()
1774 if (rtlphy->set_bwmode_inprogress) in rtl92ee_phy_sw_chnl()
1776 WARN_ONCE((rtlphy->current_channel > 14), in rtl92ee_phy_sw_chnl()
1778 rtlphy->sw_chnl_inprogress = true; in rtl92ee_phy_sw_chnl()
1779 rtlphy->sw_chnl_stage = 0; in rtl92ee_phy_sw_chnl()
1780 rtlphy->sw_chnl_step = 0; in rtl92ee_phy_sw_chnl()
1785 rtlphy->current_channel); in rtl92ee_phy_sw_chnl()
1786 rtlphy->sw_chnl_inprogress = false; in rtl92ee_phy_sw_chnl()
1790 rtlphy->sw_chnl_inprogress = false; in rtl92ee_phy_sw_chnl()
1800 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_sw_chnl_step_by_step() local
1809 u8 num_total_rfpath = rtlphy->num_total_rfpath; in _rtl92ee_phy_sw_chnl_step_by_step()
1880 rtlphy->rfreg_chnlval[rfpath] = in _rtl92ee_phy_sw_chnl_step_by_step()
1881 ((rtlphy->rfreg_chnlval[rfpath] & in _rtl92ee_phy_sw_chnl_step_by_step()
1887 rtlphy->rfreg_chnlval[rfpath]); in _rtl92ee_phy_sw_chnl_step_by_step()
2478 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_phy_iq_calibrate() local
2502 rtlphy->adda_backup, in _rtl92ee_phy_iq_calibrate()
2505 rtlphy->iqk_mac_backup); in _rtl92ee_phy_iq_calibrate()
2507 rtlphy->iqk_bb_backup, in _rtl92ee_phy_iq_calibrate()
2525 rtlphy->iqk_mac_backup); in _rtl92ee_phy_iq_calibrate()
2638 rtlphy->adda_backup, in _rtl92ee_phy_iq_calibrate()
2643 rtlphy->iqk_mac_backup); in _rtl92ee_phy_iq_calibrate()
2646 rtlphy->iqk_bb_backup, in _rtl92ee_phy_iq_calibrate()
2785 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_iq_calibrate() local
2807 rtlphy->iqk_bb_backup, 9); in rtl92ee_phy_iq_calibrate()
2866 rtlphy->reg_e94 = reg_e94; in rtl92ee_phy_iq_calibrate()
2868 rtlphy->reg_e9c = reg_e9c; in rtl92ee_phy_iq_calibrate()
2871 rtlphy->reg_eb4 = reg_eb4; in rtl92ee_phy_iq_calibrate()
2873 rtlphy->reg_ebc = reg_ebc; in rtl92ee_phy_iq_calibrate()
2878 rtlphy->reg_e94 = 0x100; in rtl92ee_phy_iq_calibrate()
2879 rtlphy->reg_eb4 = 0x100; in rtl92ee_phy_iq_calibrate()
2880 rtlphy->reg_e9c = 0x0; in rtl92ee_phy_iq_calibrate()
2881 rtlphy->reg_ebc = 0x0; in rtl92ee_phy_iq_calibrate()
2893 idx = rtl92ee_get_rightchnlplace_for_iqk(rtlphy->current_channel); in rtl92ee_phy_iq_calibrate()
2898 rtlphy->iqk_matrix[idx].value[0][i] = in rtl92ee_phy_iq_calibrate()
2901 rtlphy->iqk_matrix[idx].iqk_done = true; in rtl92ee_phy_iq_calibrate()
2904 rtlphy->iqk_bb_backup, 9); in rtl92ee_phy_iq_calibrate()
2910 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_lc_calibrate() local
2919 rtlphy->lck_inprogress = true; in rtl92ee_phy_lc_calibrate()
2926 rtlphy->lck_inprogress = false; in rtl92ee_phy_lc_calibrate()
2941 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_set_io_cmd() local
2946 iotype, rtlphy->set_io_inprogress); in rtl92ee_phy_set_io_cmd()
2965 if (postprocessing && !rtlphy->set_io_inprogress) { in rtl92ee_phy_set_io_cmd()
2966 rtlphy->set_io_inprogress = true; in rtl92ee_phy_set_io_cmd()
2967 rtlphy->current_io_type = iotype; in rtl92ee_phy_set_io_cmd()
2979 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_phy_set_io() local
2984 rtlphy->current_io_type, rtlphy->set_io_inprogress); in rtl92ee_phy_set_io()
2985 switch (rtlphy->current_io_type) { in rtl92ee_phy_set_io()
2987 rtl92ee_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1); in rtl92ee_phy_set_io()
2988 rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca); in rtl92ee_phy_set_io()
2990 rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92ee_phy_set_io()
2994 rtlphy->initgain_backup.xaagccore1 = dm_dig->cur_igvalue; in rtl92ee_phy_set_io()
2996 rtlphy->initgain_backup.cca = dm_dig->cur_cck_cca_thres; in rtl92ee_phy_set_io()
3002 rtlphy->current_io_type); in rtl92ee_phy_set_io()
3005 rtlphy->set_io_inprogress = false; in rtl92ee_phy_set_io()
3007 "(%#x)\n", rtlphy->current_io_type); in rtl92ee_phy_set_io()