139 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92ee_phy_rf_serial_read()
188 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92ee_phy_rf_serial_write()
1038 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in phy_init_bb_rf_register_def()
1039 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in phy_init_bb_rf_register_def()
1041 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1042 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1044 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1045 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1047 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =  in phy_init_bb_rf_register_def()
1049 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in phy_init_bb_rf_register_def()
1052 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;  in phy_init_bb_rf_register_def()
1053 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in phy_init_bb_rf_register_def()
1055 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;  in phy_init_bb_rf_register_def()
1056 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in phy_init_bb_rf_register_def()
1058 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;  in phy_init_bb_rf_register_def()
1059 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;  in phy_init_bb_rf_register_def()