1277 	struct rtl_phy *rtlphy = &rtlpriv->phy;  in rtl92ee_hw_init()  local
1347 	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,  in rtl92ee_hw_init()
1349 	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,  in rtl92ee_hw_init()
1351 	rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,  in rtl92ee_hw_init()
1353 	rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |  in rtl92ee_hw_init()
1357 		      rtlphy->rfreg_chnlval[0]);  in rtl92ee_hw_init()
1359 		      rtlphy->rfreg_chnlval[0]);  in rtl92ee_hw_init()
1389 		if (rtlphy->iqk_initialized) {  in rtl92ee_hw_init()
1393 			rtlphy->iqk_initialized = true;  in rtl92ee_hw_init()
1397 	rtlphy->rfpath_rx_enable[0] = true;  in rtl92ee_hw_init()
1398 	if (rtlphy->rf_type == RF_2T2R)  in rtl92ee_hw_init()
1399 		rtlphy->rfpath_rx_enable[1] = true;  in rtl92ee_hw_init()
1407 	if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {  in rtl92ee_hw_init()
1432 	struct rtl_phy *rtlphy = &rtlpriv->phy;  in _rtl92ee_read_chip_version()  local
1436 	rtlphy->rf_type = RF_2T2R;  in _rtl92ee_read_chip_version()
1445 		"Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?  in _rtl92ee_read_chip_version()
2183 	struct rtl_phy *rtlphy = &rtlpriv->phy;  in rtl92ee_read_eeprom_info()  local
2188 	if (get_rf_type(rtlphy) == RF_1T1R) {  in rtl92ee_read_eeprom_info()
2213 	rtlphy->rfpath_rx_enable[0] = true;  in rtl92ee_read_eeprom_info()
2214 	if (rtlphy->rf_type == RF_2T2R)  in rtl92ee_read_eeprom_info()
2215 		rtlphy->rfpath_rx_enable[1] = true;  in rtl92ee_read_eeprom_info()
2254 	struct rtl_phy *rtlphy = &rtlpriv->phy;  in rtl92ee_update_hal_rate_mask()  local
2310 		if (rtlphy->rf_type == RF_1T1R) {  in rtl92ee_update_hal_rate_mask()
2355 		if (rtlphy->rf_type == RF_1T1R)  in rtl92ee_update_hal_rate_mask()