Lines Matching +full:0 +full:xeb4
29 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
41 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
62 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
70 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
75 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
78 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
80 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
88 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
89 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
93 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
94 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
95 0x32c9a
99 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
100 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
181 u8 dbi_direct = 0; in rtl92d_phy_query_bb_reg()
197 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92d_phy_query_bb_reg()
207 u8 dbi_direct = 0; in rtl92d_phy_set_bb_reg()
247 u8 rfpi_enable = 0; in _rtl92d_phy_rf_serial_read()
279 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", in _rtl92d_phy_rf_serial_read()
296 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92d_phy_rf_serial_write()
298 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92d_phy_rf_serial_write()
332 if (bitmask == 0) in rtl92d_phy_set_rf_reg()
362 for (i = 0; i < arraylength; i = i + 2) in rtl92d_phy_mac_config()
366 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ in rtl92d_phy_mac_config()
369 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); in rtl92d_phy_mac_config()
372 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); in rtl92d_phy_mac_config()
383 /* 16 LSBs if read 32-bit from 0x870 */ in _rtl92d_phy_init_bb_rf_register_definition()
385 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ in _rtl92d_phy_init_bb_rf_register_definition()
387 /* 16 LSBs if read 32-bit from 0x874 */ in _rtl92d_phy_init_bb_rf_register_definition()
389 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ in _rtl92d_phy_init_bb_rf_register_definition()
393 /* 16 LSBs if read 32-bit from 0x8E0 */ in _rtl92d_phy_init_bb_rf_register_definition()
395 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ in _rtl92d_phy_init_bb_rf_register_definition()
397 /* 16 LSBs if read 32-bit from 0x8E4 */ in _rtl92d_phy_init_bb_rf_register_definition()
399 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ in _rtl92d_phy_init_bb_rf_register_definition()
403 /* 16 LSBs if read 32-bit from 0x860 */ in _rtl92d_phy_init_bb_rf_register_definition()
405 /* 16 LSBs if read 32-bit from 0x864 */ in _rtl92d_phy_init_bb_rf_register_definition()
409 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ in _rtl92d_phy_init_bb_rf_register_definition()
411 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ in _rtl92d_phy_init_bb_rf_register_definition()
511 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; in _rtl92d_phy_config_bb_with_headerfile()
516 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
540 for (i = 0; i < phy_reg_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
546 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", in _rtl92d_phy_config_bb_with_headerfile()
551 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
552 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
560 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
568 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
576 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
583 for (i = 0; i < agctab_5garraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
592 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
613 index = 0; in _rtl92d_store_pwrindex_diffrate_offset()
618 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) in _rtl92d_store_pwrindex_diffrate_offset()
634 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) in _rtl92d_store_pwrindex_diffrate_offset()
649 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", in _rtl92d_store_pwrindex_diffrate_offset()
667 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { in _rtl92d_phy_config_bb_with_pgheaderfile()
702 rtlphy->pwrgroup_cnt = 0; in _rtl92d_phy_bb_config()
717 RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl92d_phy_bb_config()
732 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92d_phy_bb_config()
733 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); in rtl92d_phy_bb_config()
734 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); in rtl92d_phy_bb_config()
735 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ in rtl92d_phy_bb_config()
741 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92d_phy_bb_config()
769 if (rtlpriv->efuse.internal_pa_5g[0]) { in rtl92d_phy_config_rf_with_headerfile()
784 * mac1 start on 5G, mac 0 has to set phy0&phy1 in rtl92d_phy_config_rf_with_headerfile()
794 for (i = 0; i < radioa_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
801 for (i = 0; i < radiob_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
820 rtlphy->default_initialgain[0] = in rtl92d_phy_get_hw_reg_originalvalue()
829 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl92d_phy_get_hw_reg_originalvalue()
830 rtlphy->default_initialgain[0], in rtl92d_phy_get_hw_reg_originalvalue()
839 "Default framesync (0x%x) = 0x%x\n", in rtl92d_phy_get_hw_reg_originalvalue()
861 cckpowerlevel[RF90_PATH_A] = 0; in _rtl92d_get_txpower_index()
862 cckpowerlevel[RF90_PATH_B] = 0; in _rtl92d_get_txpower_index()
886 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92d_ccxpower_index_check()
887 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92d_ccxpower_index_check()
914 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], in rtl92d_phy_set_txpower_level()
915 &ofdmpowerlevel[0]); in rtl92d_phy_set_txpower_level()
917 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], in rtl92d_phy_set_txpower_level()
918 &ofdmpowerlevel[0]); in rtl92d_phy_set_txpower_level()
920 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl92d_phy_set_txpower_level()
921 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); in rtl92d_phy_set_txpower_level()
931 unsigned long flag = 0; in rtl92d_phy_set_bw_mode()
957 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | in rtl92d_phy_set_bw_mode()
968 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
969 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
975 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
976 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
985 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92d_phy_set_bw_mode()
988 BIT(11), 0); in rtl92d_phy_set_bw_mode()
989 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92d_phy_set_bw_mode()
1006 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1007 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1008 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92d_phy_stop_trx_before_changeband()
1009 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92d_phy_stop_trx_before_changeband()
1041 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92d_phy_switch_wirelessband()
1042 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92d_phy_switch_wirelessband()
1047 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_switch_wirelessband()
1050 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
1053 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
1056 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
1059 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
1072 unsigned long flag = 0; in _rtl92d_phy_reload_imr_setting()
1077 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1078 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1079 /* fc area 0xd2c */ in _rtl92d_phy_reload_imr_setting()
1086 /* leave 0 for channel1-14. */ in _rtl92d_phy_reload_imr_setting()
1089 for (i = 0; i < imr_num; i++) in _rtl92d_phy_reload_imr_setting()
1092 rf_imr_param_normal[0][group][i]); in _rtl92d_phy_reload_imr_setting()
1093 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1106 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1108 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1110 for (i = 0; i < imr_num; i++) { in _rtl92d_phy_reload_imr_setting()
1114 rf_imr_param_normal[0][0][i]); in _rtl92d_phy_reload_imr_setting()
1117 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1146 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); in _rtl92d_phy_enable_rf_env()
1149 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); in _rtl92d_phy_enable_rf_env()
1153 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1155 /*Set 0 to 12 bits for 8255 */ in _rtl92d_phy_enable_rf_env()
1156 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1191 u8 index = 0, i = 0, rfpath = RF90_PATH_A; in _rtl92d_phy_switch_rf_setting()
1193 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; in _rtl92d_phy_switch_rf_setting()
1201 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
1202 for (i = 0; i < RF_CHNL_NUM_5G; i++) { in _rtl92d_phy_switch_rf_setting()
1204 index = 0; in _rtl92d_phy_switch_rf_setting()
1206 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { in _rtl92d_phy_switch_rf_setting()
1227 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { in _rtl92d_phy_switch_rf_setting()
1228 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { in _rtl92d_phy_switch_rf_setting()
1231 RFREG_OFFSET_MASK, 0xE439D); in _rtl92d_phy_switch_rf_setting()
1234 0x7FF) | (u4tmp << 11); in _rtl92d_phy_switch_rf_setting()
1247 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
1260 value = 0x07; in _rtl92d_phy_switch_rf_setting()
1262 value = 0x02; in _rtl92d_phy_switch_rf_setting()
1264 index = 0; in _rtl92d_phy_switch_rf_setting()
1278 for (i = 0; in _rtl92d_phy_switch_rf_setting()
1286 "offset 0x%x value 0x%x path %d index %d\n", in _rtl92d_phy_switch_rf_setting()
1292 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in _rtl92d_phy_switch_rf_setting()
1300 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
1303 index = 0; in _rtl92d_phy_switch_rf_setting()
1310 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_switch_rf_setting()
1320 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { in _rtl92d_phy_switch_rf_setting()
1334 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
1343 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_switch_rf_setting()
1368 return 0; in rtl92d_get_rightchnlplace_for_iqk()
1381 u8 result = 0; in _rtl92d_phy_patha_iqk()
1386 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_patha_iqk()
1387 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1388 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1390 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1391 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1393 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1394 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1397 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1398 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1399 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1400 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1404 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1407 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1408 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1415 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk()
1416 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk()
1417 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk()
1418 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk()
1419 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk()
1420 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk()
1421 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk()
1422 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk()
1423 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_patha_iqk()
1424 (((rege9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_patha_iqk()
1425 result |= 0x01; in _rtl92d_phy_patha_iqk()
1429 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_patha_iqk()
1430 (((regeac & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_patha_iqk()
1431 result |= 0x02; in _rtl92d_phy_patha_iqk()
1445 u8 result = 0; in _rtl92d_phy_patha_iqk_5g_normal()
1457 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1458 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1459 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1460 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1463 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1464 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1465 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1466 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1470 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1472 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1473 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1474 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_patha_iqk_5g_normal()
1478 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1479 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1486 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1487 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk_5g_normal()
1488 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1489 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk_5g_normal()
1490 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1491 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk_5g_normal()
1492 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1493 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk_5g_normal()
1495 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { in _rtl92d_phy_patha_iqk_5g_normal()
1496 result |= 0x01; in _rtl92d_phy_patha_iqk_5g_normal()
1505 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_patha_iqk_5g_normal()
1506 result |= 0x02; in _rtl92d_phy_patha_iqk_5g_normal()
1515 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_patha_iqk_5g_normal()
1526 u8 result = 0; in _rtl92d_phy_pathb_iqk()
1531 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1532 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1538 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1539 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk()
1540 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1541 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk()
1542 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1543 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk()
1544 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1545 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk()
1546 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1547 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk()
1548 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_pathb_iqk()
1549 (((regebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_pathb_iqk()
1550 result |= 0x01; in _rtl92d_phy_pathb_iqk()
1553 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_pathb_iqk()
1554 (((regecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_pathb_iqk()
1555 result |= 0x02; in _rtl92d_phy_pathb_iqk()
1567 u8 result = 0; in _rtl92d_phy_pathb_iqk_5g_normal()
1574 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1575 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1576 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1577 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1580 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1581 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1582 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1583 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1587 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1590 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1591 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1593 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_pathb_iqk_5g_normal()
1597 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1598 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1606 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1607 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk_5g_normal()
1608 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1609 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk_5g_normal()
1610 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1611 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk_5g_normal()
1612 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1613 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk_5g_normal()
1614 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1615 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk_5g_normal()
1617 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) in _rtl92d_phy_pathb_iqk_5g_normal()
1618 result |= 0x01; in _rtl92d_phy_pathb_iqk_5g_normal()
1622 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_pathb_iqk_5g_normal()
1623 result |= 0x02; in _rtl92d_phy_pathb_iqk_5g_normal()
1633 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_pathb_iqk_5g_normal()
1647 for (i = 0; i < regnum; i++) in _rtl92d_phy_save_adda_registers()
1658 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92d_phy_save_mac_registers()
1672 for (i = 0; i < regnum; i++) in _rtl92d_phy_reload_adda_registers()
1683 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92d_phy_reload_mac_registers()
1696 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; in _rtl92d_phy_path_adda_on()
1698 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? in _rtl92d_phy_path_adda_on()
1699 0x04db25a4 : 0x0b1b25a4; in _rtl92d_phy_path_adda_on()
1700 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in _rtl92d_phy_path_adda_on()
1711 rtl_write_byte(rtlpriv, macreg[0], 0x3F); in _rtl92d_phy_mac_setting_calibration()
1724 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1725 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1726 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1736 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl92d_phy_pimode_switch()
1737 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1738 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1749 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate()
1750 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate()
1751 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate()
1752 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate()
1755 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate()
1768 if (t == 0) { in _rtl92d_phy_iq_calibrate()
1770 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate()
1783 if (t == 0) in _rtl92d_phy_iq_calibrate()
1791 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate()
1792 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1793 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1794 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1795 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate()
1798 0x00010000); in _rtl92d_phy_iq_calibrate()
1800 0x00010000); in _rtl92d_phy_iq_calibrate()
1806 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1808 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1811 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1812 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1813 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1814 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1816 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1819 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1820 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1821 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1822 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1823 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1824 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1825 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1826 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1828 } else if (i == (retrycount - 1) && patha_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1833 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1834 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1835 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1836 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1839 if (0x00 == patha_ok) in _rtl92d_phy_iq_calibrate()
1845 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1847 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1850 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1851 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1852 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1853 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1854 result[t][6] = (rtl_get_bbreg(hw, 0xec4, in _rtl92d_phy_iq_calibrate()
1855 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1856 result[t][7] = (rtl_get_bbreg(hw, 0xecc, in _rtl92d_phy_iq_calibrate()
1857 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1859 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1863 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1864 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1865 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1866 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1869 if (0x00 == pathb_ok) in _rtl92d_phy_iq_calibrate()
1878 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1879 if (t != 0) { in _rtl92d_phy_iq_calibrate()
1897 /* load 0xe30 IQC default value */ in _rtl92d_phy_iq_calibrate()
1898 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1899 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1912 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate_5g_normal()
1913 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate_5g_normal()
1914 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate_5g_normal()
1915 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate_5g_normal()
1918 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate_5g_normal()
1935 if (t == 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
1937 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate_5g_normal()
1959 if (t == 0) in _rtl92d_phy_iq_calibrate_5g_normal()
1965 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate_5g_normal()
1966 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1967 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1968 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1969 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate_5g_normal()
1972 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1974 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1977 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1978 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1979 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
1981 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
1983 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1984 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1985 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1986 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1987 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1988 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1989 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1990 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1991 } else if (patha_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
1995 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1996 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1997 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1998 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2007 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
2010 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2011 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2012 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2013 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2014 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2015 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2016 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2017 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2018 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
2021 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2022 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2023 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2024 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2034 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2035 if (t != 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
2064 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ in _rtl92d_phy_simularity_compare()
2072 sim_bitmap = 0; in _rtl92d_phy_simularity_compare()
2073 for (i = 0; i < bound; i++) { in _rtl92d_phy_simularity_compare()
2078 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92d_phy_simularity_compare()
2080 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92d_phy_simularity_compare()
2089 if (sim_bitmap == 0) { in _rtl92d_phy_simularity_compare()
2090 for (i = 0; i < (bound / 4); i++) { in _rtl92d_phy_simularity_compare()
2091 if (final_candidate[i] != 0xFF) { in _rtl92d_phy_simularity_compare()
2100 if (!(sim_bitmap & 0x0F)) { /* path A OK */ in _rtl92d_phy_simularity_compare()
2101 for (i = 0; i < 4; i++) in _rtl92d_phy_simularity_compare()
2103 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ in _rtl92d_phy_simularity_compare()
2104 for (i = 0; i < 2; i++) in _rtl92d_phy_simularity_compare()
2107 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ in _rtl92d_phy_simularity_compare()
2110 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ in _rtl92d_phy_simularity_compare()
2130 if (final_candidate == 0xFF) { in _rtl92d_phy_patha_fill_iqk_matrix()
2134 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ in _rtl92d_phy_patha_fill_iqk_matrix()
2135 val_x = result[final_candidate][0]; in _rtl92d_phy_patha_fill_iqk_matrix()
2136 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
2137 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
2140 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2142 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92d_phy_patha_fill_iqk_matrix()
2144 ((val_x * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
2146 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
2147 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
2154 "Y = 0x%lx, tx0_c = 0x%lx\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2156 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92d_phy_patha_fill_iqk_matrix()
2157 ((tx0_c & 0x3C0) >> 6)); in _rtl92d_phy_patha_fill_iqk_matrix()
2158 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_patha_fill_iqk_matrix()
2159 (tx0_c & 0x3F)); in _rtl92d_phy_patha_fill_iqk_matrix()
2162 ((val_y * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
2163 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2171 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2172 reg = result[final_candidate][3] & 0x3F; in _rtl92d_phy_patha_fill_iqk_matrix()
2173 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2174 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92d_phy_patha_fill_iqk_matrix()
2175 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2189 if (final_candidate == 0xFF) { in _rtl92d_phy_pathb_fill_iqk_matrix()
2193 MASKDWORD) >> 22) & 0x3FF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2195 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
2196 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
2198 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
2200 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92d_phy_pathb_fill_iqk_matrix()
2202 ((val_x * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2204 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
2205 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
2209 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
2211 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2212 ((tx1_c & 0x3C0) >> 6)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2213 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2214 (tx1_c & 0x3F)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2216 ((val_y * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2220 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2221 reg = result[final_candidate][7] & 0x3F; in _rtl92d_phy_pathb_fill_iqk_matrix()
2222 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2223 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2224 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2237 long regebc, regec4, regecc, regtmp = 0; in rtl92d_phy_iq_calibrate()
2239 unsigned long flag = 0; in rtl92d_phy_iq_calibrate()
2243 for (i = 0; i < 8; i++) { in rtl92d_phy_iq_calibrate()
2244 result[0][i] = 0; in rtl92d_phy_iq_calibrate()
2245 result[1][i] = 0; in rtl92d_phy_iq_calibrate()
2246 result[2][i] = 0; in rtl92d_phy_iq_calibrate()
2247 result[3][i] = 0; in rtl92d_phy_iq_calibrate()
2249 final_candidate = 0xff; in rtl92d_phy_iq_calibrate()
2258 for (i = 0; i < 3; i++) { in rtl92d_phy_iq_calibrate()
2269 0, 1); in rtl92d_phy_iq_calibrate()
2271 final_candidate = 0; in rtl92d_phy_iq_calibrate()
2277 0, 2); in rtl92d_phy_iq_calibrate()
2279 final_candidate = 0; in rtl92d_phy_iq_calibrate()
2287 for (i = 0; i < 8; i++) in rtl92d_phy_iq_calibrate()
2290 if (regtmp != 0) in rtl92d_phy_iq_calibrate()
2293 final_candidate = 0xFF; in rtl92d_phy_iq_calibrate()
2298 for (i = 0; i < 4; i++) { in rtl92d_phy_iq_calibrate()
2299 rege94 = result[i][0]; in rtl92d_phy_iq_calibrate()
2312 if (final_candidate != 0xff) { in rtl92d_phy_iq_calibrate()
2313 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; in rtl92d_phy_iq_calibrate()
2329 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ in rtl92d_phy_iq_calibrate()
2330 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ in rtl92d_phy_iq_calibrate()
2332 if ((rege94 != 0) /*&&(regea4 != 0) */) in rtl92d_phy_iq_calibrate()
2334 final_candidate, (regea4 == 0)); in rtl92d_phy_iq_calibrate()
2336 if ((regeb4 != 0) /*&&(regec4 != 0) */) in rtl92d_phy_iq_calibrate()
2338 final_candidate, (regec4 == 0)); in rtl92d_phy_iq_calibrate()
2340 if (final_candidate != 0xFF) { in rtl92d_phy_iq_calibrate()
2344 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl92d_phy_iq_calibrate()
2346 value[0][i] = result[final_candidate][i]; in rtl92d_phy_iq_calibrate()
2368 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && in rtl92d_phy_reload_iqk_setting()
2378 indexforchannel == 0) || indexforchannel > 0) { in rtl92d_phy_reload_iqk_setting()
2382 if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) in rtl92d_phy_reload_iqk_setting()
2384 rtlphy->iqk_matrix[indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
2385 rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); in rtl92d_phy_reload_iqk_setting()
2388 indexforchannel].value[0][4] != 0) in rtl92d_phy_reload_iqk_setting()
2389 /*&&(regec4 != 0) */) in rtl92d_phy_reload_iqk_setting()
2393 indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
2395 indexforchannel].value[0][6] in rtl92d_phy_reload_iqk_setting()
2396 == 0)); in rtl92d_phy_reload_iqk_setting()
2420 for (i = 0; i < ARRAY_SIZE(channel5g); i++) in _rtl92d_is_legal_5g_channel()
2431 u32 smallest_abs_val = 0xffffffff, u4tmp; in _rtl92d_phy_calc_curvindex()
2435 for (i = 0; i < chnl_num; i++) { in _rtl92d_phy_calc_curvindex()
2438 curveindex[i] = 0; in _rtl92d_phy_calc_curvindex()
2439 for (j = 0; j < (CV_CURVE_CNT * 2); j++) { in _rtl92d_phy_calc_curvindex()
2448 smallest_abs_val = 0xffffffff; in _rtl92d_phy_calc_curvindex()
2462 u32 u4tmp = 0, u4regvalue = 0; in _rtl92d_phy_reload_lck_setting()
2472 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
2483 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
2491 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
2493 rtlpriv->rtlhal.interfaceindex == 0) { in _rtl92d_phy_reload_lck_setting()
2501 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
2503 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_reload_lck_setting()
2504 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); in _rtl92d_phy_reload_lck_setting()
2522 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; in _rtl92d_phy_lc_calibrate_sw()
2523 u16 timeout = 800, timecount = 0; in _rtl92d_phy_lc_calibrate_sw()
2526 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl92d_phy_lc_calibrate_sw()
2529 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
2530 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl92d_phy_lc_calibrate_sw()
2532 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_lc_calibrate_sw()
2533 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92d_phy_lc_calibrate_sw()
2534 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
2536 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
2540 RFREG_OFFSET_MASK, 0x010000); in _rtl92d_phy_lc_calibrate_sw()
2544 BIT(17), 0x0); in _rtl92d_phy_lc_calibrate_sw()
2547 0x08000, 0x01); in _rtl92d_phy_lc_calibrate_sw()
2560 if (index == 0 && rtlhal->interfaceindex == 0) { in _rtl92d_phy_lc_calibrate_sw()
2567 memset(curvecount_val, 0, sizeof(curvecount_val)); in _rtl92d_phy_lc_calibrate_sw()
2570 0x08000, 0x0); in _rtl92d_phy_lc_calibrate_sw()
2571 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); in _rtl92d_phy_lc_calibrate_sw()
2573 for (i = 0; i < CV_CURVE_CNT; i++) { in _rtl92d_phy_lc_calibrate_sw()
2574 u32 readval = 0, readval2 = 0; in _rtl92d_phy_lc_calibrate_sw()
2575 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, in _rtl92d_phy_lc_calibrate_sw()
2576 0x7f, i); in _rtl92d_phy_lc_calibrate_sw()
2578 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, in _rtl92d_phy_lc_calibrate_sw()
2579 RFREG_OFFSET_MASK, 0x0); in _rtl92d_phy_lc_calibrate_sw()
2581 0x4F, RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
2582 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; in _rtl92d_phy_lc_calibrate_sw()
2583 /* reg 0x4f [4:0] */ in _rtl92d_phy_lc_calibrate_sw()
2584 /* reg 0x50 [19:10] */ in _rtl92d_phy_lc_calibrate_sw()
2586 0x50, 0xffc00); in _rtl92d_phy_lc_calibrate_sw()
2587 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | in _rtl92d_phy_lc_calibrate_sw()
2590 if (index == 0 && rtlhal->interfaceindex == 0) in _rtl92d_phy_lc_calibrate_sw()
2600 BIT(17), 0x1); in _rtl92d_phy_lc_calibrate_sw()
2604 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
2605 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
2606 rtl_write_byte(rtlpriv, offset, 0x50); in _rtl92d_phy_lc_calibrate_sw()
2609 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
2610 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl92d_phy_lc_calibrate_sw()
2612 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2613 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2630 u32 timeout = 2000, timecount = 0; in rtl92d_phy_lc_calibrate()
2687 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ in rtl92d_phy_reset_iqk_result()
2688 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { in rtl92d_phy_reset_iqk_result()
2689 rtlphy->iqk_matrix[i].value[0][0] = 0x100; in rtl92d_phy_reset_iqk_result()
2690 rtlphy->iqk_matrix[i].value[0][2] = 0x100; in rtl92d_phy_reset_iqk_result()
2691 rtlphy->iqk_matrix[i].value[0][4] = 0x100; in rtl92d_phy_reset_iqk_result()
2692 rtlphy->iqk_matrix[i].value[0][6] = 0x100; in rtl92d_phy_reset_iqk_result()
2693 rtlphy->iqk_matrix[i].value[0][1] = 0x0; in rtl92d_phy_reset_iqk_result()
2694 rtlphy->iqk_matrix[i].value[0][3] = 0x0; in rtl92d_phy_reset_iqk_result()
2695 rtlphy->iqk_matrix[i].value[0][5] = 0x0; in rtl92d_phy_reset_iqk_result()
2696 rtlphy->iqk_matrix[i].value[0][7] = 0x0; in rtl92d_phy_reset_iqk_result()
2717 precommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2720 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2722 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2723 postcommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2725 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2726 rfdependcmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2729 RF_CHNLBW, channel, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2732 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2736 case 0: in _rtl92d_phy_sw_chnl_step_by_step()
2751 (*step) = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2772 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92d_phy_sw_chnl_step_by_step()
2775 0xffffff00) | currentcmd->para2); in _rtl92d_phy_sw_chnl_step_by_step()
2821 u32 timeout = 1000, timecount = 0; in rtl92d_phy_sw_chnl()
2826 return 0; in rtl92d_phy_sw_chnl()
2828 return 0; in rtl92d_phy_sw_chnl()
2833 return 0; in rtl92d_phy_sw_chnl()
2843 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2845 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2853 return 0; in rtl92d_phy_sw_chnl()
2859 return 0; in rtl92d_phy_sw_chnl()
2867 if (channel == 0) in rtl92d_phy_sw_chnl()
2869 rtlphy->sw_chnl_stage = 0; in rtl92d_phy_sw_chnl()
2870 rtlphy->sw_chnl_step = 0; in rtl92d_phy_sw_chnl()
2880 if (delay > 0) in rtl92d_phy_sw_chnl()
2911 de_digtable->cur_igvalue = 0x37; in rtl92d_phy_set_io()
2966 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ in _rtl92d_phy_set_rfon()
2967 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ in _rtl92d_phy_set_rfon()
2969 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92d_phy_set_rfon()
2970 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ in _rtl92d_phy_set_rfon()
2971 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2973 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ in _rtl92d_phy_set_rfon()
2974 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfon()
2975 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ in _rtl92d_phy_set_rfon()
2976 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ in _rtl92d_phy_set_rfon()
2977 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfon()
2978 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2979 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ in _rtl92d_phy_set_rfon()
2980 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfon()
2989 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ in _rtl92d_phy_set_rfsleep()
2990 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_set_rfsleep()
2991 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ in _rtl92d_phy_set_rfsleep()
2992 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
2993 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ in _rtl92d_phy_set_rfsleep()
2994 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
2995 /* d. APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
2996 * APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
2997 * RF path 0 offset 0x00 = 0x00 in _rtl92d_phy_set_rfsleep()
2998 * APSD_CTRL 0x600[7:0] = 0x40 in _rtl92d_phy_set_rfsleep()
3000 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3001 while (u4btmp != 0 && delay > 0) { in _rtl92d_phy_set_rfsleep()
3002 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl92d_phy_set_rfsleep()
3003 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
3004 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
3005 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3008 if (delay == 0) { in _rtl92d_phy_set_rfsleep()
3010 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfsleep()
3012 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3013 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfsleep()
3014 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfsleep()
3019 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ in _rtl92d_phy_set_rfsleep()
3020 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3021 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ in _rtl92d_phy_set_rfsleep()
3023 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92d_phy_set_rfsleep()
3024 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ in _rtl92d_phy_set_rfsleep()
3047 u32 initializecount = 0; in rtl92d_phy_set_rf_power_state()
3093 for (queue_id = 0, i = 0; in rtl92d_phy_set_rf_power_state()
3096 if (skb_queue_len(&ring->queue) == 0 || in rtl92d_phy_set_rf_power_state()
3102 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", in rtl92d_phy_set_rf_power_state()
3154 rtl_write_byte(rtlpriv, offset, 0xF3); in rtl92d_phy_config_macphymode()
3159 rtl_write_byte(rtlpriv, offset, 0xF4); in rtl92d_phy_config_macphymode()
3164 rtl_write_byte(rtlpriv, offset, 0xF1); in rtl92d_phy_config_macphymode()
3194 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_config_macphymode_info()
3212 group = 0; in rtl92d_get_chnlgroup_fromarray()
3245 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); in rtl92d_phy_set_poweron()
3247 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_set_poweron()
3263 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_set_poweron()
3272 for (i = 0; i < 200; i++) { in rtl92d_phy_set_poweron()
3273 if ((value8 & BIT(7)) == 0) { in rtl92d_phy_set_poweron()
3295 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3296 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3297 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); in rtl92d_phy_config_maccoexist_rfpage()
3300 rtl_write_byte(rtlpriv, REG_DMC, 0xf8); in rtl92d_phy_config_maccoexist_rfpage()
3301 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3302 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); in rtl92d_phy_config_maccoexist_rfpage()
3305 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3306 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); in rtl92d_phy_config_maccoexist_rfpage()
3307 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); in rtl92d_phy_config_maccoexist_rfpage()
3323 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ in rtl92d_update_bbrf_configuration()
3325 /* r_select_5G for path_A/B,0x878 */ in rtl92d_update_bbrf_configuration()
3326 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
3327 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
3329 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
3330 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
3332 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ in rtl92d_update_bbrf_configuration()
3333 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92d_update_bbrf_configuration()
3334 /* fc_area 0xd2c */ in rtl92d_update_bbrf_configuration()
3335 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92d_update_bbrf_configuration()
3337 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92d_update_bbrf_configuration()
3338 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
3340 0x40000100); in rtl92d_update_bbrf_configuration()
3342 0x40000100); in rtl92d_update_bbrf_configuration()
3352 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
3353 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
3354 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
3368 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
3369 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
3376 BIT(31) | BIT(15), 0); in rtl92d_update_bbrf_configuration()
3381 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
3382 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
3384 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
3385 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
3387 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ in rtl92d_update_bbrf_configuration()
3388 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92d_update_bbrf_configuration()
3390 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92d_update_bbrf_configuration()
3392 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92d_update_bbrf_configuration()
3393 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
3394 if (rtlefuse->internal_pa_5g[0]) in rtl92d_update_bbrf_configuration()
3396 0x2d4000b5); in rtl92d_update_bbrf_configuration()
3399 0x20000080); in rtl92d_update_bbrf_configuration()
3402 0x2d4000b5); in rtl92d_update_bbrf_configuration()
3405 0x20000080); in rtl92d_update_bbrf_configuration()
3431 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3432 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3433 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3435 BIT(26) | BIT(24), 0x00); in rtl92d_update_bbrf_configuration()
3436 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3437 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3438 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92d_update_bbrf_configuration()
3444 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
3446 BIT(18), 0); in rtl92d_update_bbrf_configuration()
3448 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in rtl92d_update_bbrf_configuration()
3449 0x1c000, 0x07); in rtl92d_update_bbrf_configuration()
3451 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
3460 /* Use antenna 0,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
3461 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92d_update_bbrf_configuration()
3462 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92d_update_bbrf_configuration()
3465 if (rtlhal->interfaceindex == 0) { in rtl92d_update_bbrf_configuration()
3467 BIT(13), 0x3); in rtl92d_update_bbrf_configuration()
3471 "MAC1 use DBI to update 0x888\n"); in rtl92d_update_bbrf_configuration()
3472 /* 0x888 */ in rtl92d_update_bbrf_configuration()
3482 /* Use antenna 0 & 1,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
3483 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92d_update_bbrf_configuration()
3484 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92d_update_bbrf_configuration()
3485 /* disable ad/da clock1,0x888 */ in rtl92d_update_bbrf_configuration()
3486 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92d_update_bbrf_configuration()
3492 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, in rtl92d_update_bbrf_configuration()
3495 for (i = 0; i < 2; i++) in rtl92d_update_bbrf_configuration()
3496 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", in rtl92d_update_bbrf_configuration()
3515 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_check_poweroff()