Lines Matching refs:rtlpriv
22 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_read_dword_dbi() local
25 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); in rtl92de_read_dword_dbi()
26 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct); in rtl92de_read_dword_dbi()
28 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA); in rtl92de_read_dword_dbi()
35 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_write_dword_dbi() local
37 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); in rtl92de_write_dword_dbi()
38 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value); in rtl92de_write_dword_dbi()
39 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); in rtl92de_write_dword_dbi()
46 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_set_bcn_ctrl_reg() local
50 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); in _rtl92de_set_bcn_ctrl_reg()
55 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_stop_tx_beacon() local
58 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); in _rtl92de_stop_tx_beacon()
59 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); in _rtl92de_stop_tx_beacon()
60 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in _rtl92de_stop_tx_beacon()
61 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92de_stop_tx_beacon()
62 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); in _rtl92de_stop_tx_beacon()
64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); in _rtl92de_stop_tx_beacon()
69 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_resume_tx_beacon() local
72 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); in _rtl92de_resume_tx_beacon()
73 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); in _rtl92de_resume_tx_beacon()
74 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in _rtl92de_resume_tx_beacon()
75 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92de_resume_tx_beacon()
76 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); in _rtl92de_resume_tx_beacon()
78 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); in _rtl92de_resume_tx_beacon()
93 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_get_hw_reg() local
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, in rtl92de_get_hw_reg()
113 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); in rtl92de_get_hw_reg()
130 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); in rtl92de_get_hw_reg()
131 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); in rtl92de_get_hw_reg()
136 *((bool *)(val)) = rtlpriv->dm.interrupt_migration; in rtl92de_get_hw_reg()
139 *((bool *)(val)) = rtlpriv->dm.disable_tx_int; in rtl92de_get_hw_reg()
151 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_hw_reg() local
162 rtl_write_byte(rtlpriv, (REG_MACID + idx), in rtl92de_set_hw_reg()
174 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); in rtl92de_set_hw_reg()
175 rtl_write_byte(rtlpriv, REG_RRSR + 1, in rtl92de_set_hw_reg()
182 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, in rtl92de_set_hw_reg()
188 rtl_write_byte(rtlpriv, (REG_BSSID + idx), in rtl92de_set_hw_reg()
193 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); in rtl92de_set_hw_reg()
194 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); in rtl92de_set_hw_reg()
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); in rtl92de_set_hw_reg()
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); in rtl92de_set_hw_reg()
198 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, in rtl92de_set_hw_reg()
201 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, in rtl92de_set_hw_reg()
207 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
209 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); in rtl92de_set_hw_reg()
211 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92de_set_hw_reg()
223 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); in rtl92de_set_hw_reg()
238 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
241 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, in rtl92de_set_hw_reg()
250 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; in rtl92de_set_hw_reg()
252 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
255 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, in rtl92de_set_hw_reg()
286 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset); in rtl92de_set_hw_reg()
287 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
297 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, in rtl92de_set_hw_reg()
306 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); in rtl92de_set_hw_reg()
321 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, in rtl92de_set_hw_reg()
343 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, in rtl92de_set_hw_reg()
346 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); in rtl92de_set_hw_reg()
350 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92de_set_hw_reg()
356 rtl_write_word(rtlpriv, REG_RL, in rtl92de_set_hw_reg()
362 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); in rtl92de_set_hw_reg()
374 rtl_write_byte(rtlpriv, REG_SECCFG, *val); in rtl92de_set_hw_reg()
390 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92de_set_hw_reg()
392 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); in rtl92de_set_hw_reg()
393 rtl_write_byte(rtlpriv, REG_CR + 1, in rtl92de_set_hw_reg()
397 tmp_reg422 = rtl_read_byte(rtlpriv, in rtl92de_set_hw_reg()
401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, in rtl92de_set_hw_reg()
407 rtl_write_byte(rtlpriv, in rtl92de_set_hw_reg()
410 rtl_write_byte(rtlpriv, REG_CR + 1, in rtl92de_set_hw_reg()
418 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); in rtl92de_set_hw_reg()
420 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | in rtl92de_set_hw_reg()
430 rtl_write_dword(rtlpriv, REG_TSFTR, in rtl92de_set_hw_reg()
432 rtl_write_dword(rtlpriv, REG_TSFTR + 4, in rtl92de_set_hw_reg()
448 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0); in rtl92de_set_hw_reg()
449 rtlpriv->dm.interrupt_migration = int_migration; in rtl92de_set_hw_reg()
452 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in rtl92de_set_hw_reg()
453 rtlpriv->dm.interrupt_migration = int_migration; in rtl92de_set_hw_reg()
467 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, in rtl92de_set_hw_reg()
469 rtlpriv->dm.disable_tx_int = disable_ac_int; in rtl92de_set_hw_reg()
472 rtlpriv->cfg->ops->update_interrupt_mask(hw, in rtl92de_set_hw_reg()
474 rtlpriv->dm.disable_tx_int = disable_ac_int; in rtl92de_set_hw_reg()
486 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_llt_write() local
492 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); in _rtl92de_llt_write()
494 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); in _rtl92de_llt_write()
509 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_llt_table_init() local
517 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { in _rtl92de_llt_table_init()
532 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); in _rtl92de_llt_table_init()
533 rtl_write_dword(rtlpriv, REG_RQPN, value32); in _rtl92de_llt_table_init()
537 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, in _rtl92de_llt_table_init()
538 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 | in _rtl92de_llt_table_init()
543 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); in _rtl92de_llt_table_init()
547 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); in _rtl92de_llt_table_init()
548 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); in _rtl92de_llt_table_init()
552 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); in _rtl92de_llt_table_init()
558 rtl_write_byte(rtlpriv, REG_PBP, 0x11); in _rtl92de_llt_table_init()
561 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); in _rtl92de_llt_table_init()
595 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_gen_refresh_led_state() local
598 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; in _rtl92de_gen_refresh_led_state()
612 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_init_mac() local
623 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); in _rtl92de_init_mac()
624 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05); in _rtl92de_init_mac()
632 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92de_init_mac()
635 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); in _rtl92de_init_mac()
642 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); in _rtl92de_init_mac()
644 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); in _rtl92de_init_mac()
648 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); in _rtl92de_init_mac()
653 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); in _rtl92de_init_mac()
659 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); in _rtl92de_init_mac()
664 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); in _rtl92de_init_mac()
671 rtl_write_word(rtlpriv, REG_CR, 0x0); in _rtl92de_init_mac()
674 rtl_write_word(rtlpriv, REG_CR, 0x2ff); in _rtl92de_init_mac()
677 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0); in _rtl92de_init_mac()
689 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); in _rtl92de_init_mac()
690 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); in _rtl92de_init_mac()
708 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); in _rtl92de_init_mac()
711 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); in _rtl92de_init_mac()
716 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); in _rtl92de_init_mac()
723 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); in _rtl92de_init_mac()
727 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); in _rtl92de_init_mac()
730 rtl_write_byte(rtlpriv, 0x4d0, 0x0); in _rtl92de_init_mac()
733 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, in _rtl92de_init_mac()
735 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma); in _rtl92de_init_mac()
736 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma); in _rtl92de_init_mac()
737 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma); in _rtl92de_init_mac()
738 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma); in _rtl92de_init_mac()
739 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma); in _rtl92de_init_mac()
740 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma); in _rtl92de_init_mac()
742 rtl_write_dword(rtlpriv, REG_RX_DESA, in _rtl92de_init_mac()
748 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33); in _rtl92de_init_mac()
751 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in _rtl92de_init_mac()
754 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); in _rtl92de_init_mac()
755 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); in _rtl92de_init_mac()
758 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); in _rtl92de_init_mac()
765 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); in _rtl92de_init_mac()
773 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_hw_configure() local
779 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); in _rtl92de_hw_configure()
780 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); in _rtl92de_hw_configure()
781 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); in _rtl92de_hw_configure()
782 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in _rtl92de_hw_configure()
783 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); in _rtl92de_hw_configure()
784 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); in _rtl92de_hw_configure()
785 rtl_write_word(rtlpriv, REG_RL, 0x0707); in _rtl92de_hw_configure()
786 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); in _rtl92de_hw_configure()
787 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); in _rtl92de_hw_configure()
788 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); in _rtl92de_hw_configure()
789 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
790 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); in _rtl92de_hw_configure()
791 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
794 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641); in _rtl92de_hw_configure()
796 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641); in _rtl92de_hw_configure()
798 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); in _rtl92de_hw_configure()
799 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); in _rtl92de_hw_configure()
800 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in _rtl92de_hw_configure()
802 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); in _rtl92de_hw_configure()
803 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92de_hw_configure()
804 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); in _rtl92de_hw_configure()
805 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); in _rtl92de_hw_configure()
806 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); in _rtl92de_hw_configure()
808 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666); in _rtl92de_hw_configure()
810 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); in _rtl92de_hw_configure()
812 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
813 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
815 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); in _rtl92de_hw_configure()
817 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); in _rtl92de_hw_configure()
819 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); in _rtl92de_hw_configure()
820 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); in _rtl92de_hw_configure()
821 switch (rtlpriv->phy.rf_type) { in _rtl92de_hw_configure()
835 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_enable_aspm_back_door() local
838 rtl_write_byte(rtlpriv, 0x34b, 0x93); in _rtl92de_enable_aspm_back_door()
839 rtl_write_word(rtlpriv, 0x350, 0x870c); in _rtl92de_enable_aspm_back_door()
840 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
842 rtl_write_byte(rtlpriv, 0x349, 0x1b); in _rtl92de_enable_aspm_back_door()
844 rtl_write_byte(rtlpriv, 0x349, 0x03); in _rtl92de_enable_aspm_back_door()
845 rtl_write_word(rtlpriv, 0x350, 0x2718); in _rtl92de_enable_aspm_back_door()
846 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
851 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_enable_hw_security_config() local
854 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in rtl92de_enable_hw_security_config()
856 rtlpriv->sec.pairwise_enc_algorithm, in rtl92de_enable_hw_security_config()
857 rtlpriv->sec.group_enc_algorithm); in rtl92de_enable_hw_security_config()
858 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { in rtl92de_enable_hw_security_config()
859 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_enable_hw_security_config()
864 if (rtlpriv->sec.use_defaultkey) { in rtl92de_enable_hw_security_config()
869 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); in rtl92de_enable_hw_security_config()
870 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_enable_hw_security_config()
872 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); in rtl92de_enable_hw_security_config()
877 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_hw_init() local
880 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92de_hw_init()
905 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, in rtl92de_hw_init()
910 rtlpriv->psc.fw_current_inpsmode = false; in rtl92de_hw_init()
912 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
914 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
917 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in rtl92de_hw_init()
920 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0); in rtl92de_hw_init()
922 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b); in rtl92de_hw_init()
924 rtl_write_byte(rtlpriv, 0x4d3, 0x80); in rtl92de_hw_init()
926 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
928 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
932 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); in rtl92de_hw_init()
933 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); in rtl92de_hw_init()
934 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); in rtl92de_hw_init()
942 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); in rtl92de_hw_init()
993 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); in rtl92de_hw_init()
1029 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_chip_version() local
1033 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); in _rtl92de_read_chip_version()
1036 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); in _rtl92de_read_chip_version()
1039 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); in _rtl92de_read_chip_version()
1047 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_set_media_status() local
1048 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); in _rtl92de_set_media_status()
1062 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, in _rtl92de_set_media_status()
1070 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1075 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1081 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1086 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1093 rtl_write_byte(rtlpriv, MSR, bt_msr); in _rtl92de_set_media_status()
1094 rtlpriv->cfg->ops->led_control(hw, ledaction); in _rtl92de_set_media_status()
1096 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92de_set_media_status()
1098 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92de_set_media_status()
1104 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_check_bssid() local
1107 if (rtlpriv->psc.rfpwr_state != ERFON) in rtl92de_set_check_bssid()
1110 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
1114 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
1119 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
1125 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_network_type() local
1131 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { in rtl92de_set_network_type()
1146 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92d_linked_set_reg() local
1147 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_linked_set_reg()
1153 rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG, in rtl92d_linked_set_reg()
1168 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_enable_interrupt() local
1171 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
1172 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
1178 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_disable_interrupt() local
1181 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); in rtl92de_disable_interrupt()
1182 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); in rtl92de_disable_interrupt()
1188 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_poweroff_adapter() local
1192 rtlpriv->intf_ops->enable_aspm(hw); in _rtl92de_poweroff_adapter()
1193 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); in _rtl92de_poweroff_adapter()
1198 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); in _rtl92de_poweroff_adapter()
1204 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); in _rtl92de_poweroff_adapter()
1207 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in _rtl92de_poweroff_adapter()
1212 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); in _rtl92de_poweroff_adapter()
1215 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); in _rtl92de_poweroff_adapter()
1219 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, in _rtl92de_poweroff_adapter()
1223 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); in _rtl92de_poweroff_adapter()
1226 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); in _rtl92de_poweroff_adapter()
1231 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); in _rtl92de_poweroff_adapter()
1234 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); in _rtl92de_poweroff_adapter()
1237 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
1240 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
1250 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); in _rtl92de_poweroff_adapter()
1252 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92de_poweroff_adapter()
1254 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL)); in _rtl92de_poweroff_adapter()
1259 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { in _rtl92de_poweroff_adapter()
1261 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); in _rtl92de_poweroff_adapter()
1263 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp); in _rtl92de_poweroff_adapter()
1267 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n"); in _rtl92de_poweroff_adapter()
1272 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_card_disable() local
1284 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); in rtl92de_card_disable()
1294 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); in rtl92de_card_disable()
1305 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in rtl92de_card_disable()
1312 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92de_card_disable()
1316 if (rtlpriv->rtlhal.interfaceindex == 1) in rtl92de_card_disable()
1317 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); in rtl92de_card_disable()
1322 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); in rtl92de_card_disable()
1324 rtl_write_byte(rtlpriv, REG_CR, 0x0); in rtl92de_card_disable()
1325 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n"); in rtl92de_card_disable()
1334 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_interrupt_recognized() local
1337 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92de_interrupt_recognized()
1338 rtl_write_dword(rtlpriv, ISR, intvec->inta); in rtl92de_interrupt_recognized()
1343 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_beacon_related_registers() local
1350 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); in rtl92de_set_beacon_related_registers()
1351 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); in rtl92de_set_beacon_related_registers()
1352 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); in rtl92de_set_beacon_related_registers()
1353 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); in rtl92de_set_beacon_related_registers()
1354 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) in rtl92de_set_beacon_related_registers()
1355 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); in rtl92de_set_beacon_related_registers()
1357 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); in rtl92de_set_beacon_related_registers()
1358 rtl_write_byte(rtlpriv, 0x606, 0x30); in rtl92de_set_beacon_related_registers()
1363 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_beacon_interval() local
1367 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, in rtl92de_set_beacon_interval()
1370 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); in rtl92de_set_beacon_interval()
1377 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_interrupt_mask() local
1380 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", in rtl92de_update_interrupt_mask()
1535 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_txpower_info() local
1551 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || in _rtl92de_read_txpower_info()
1552 IS_92D_E_CUT(rtlpriv->rtlhal.version)) { in _rtl92de_read_txpower_info()
1557 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, in _rtl92de_read_txpower_info()
1609 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1611 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1613 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1615 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1646 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_macphymode_from_prom() local
1652 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92de_read_macphymode_from_prom()
1656 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92de_read_macphymode_from_prom()
1671 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_efuse_update_chip_version() local
1672 enum version_8192d chipver = rtlpriv->rtlhal.version; in _rtl92de_efuse_update_chip_version()
1676 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, in _rtl92de_efuse_update_chip_version()
1678 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, in _rtl92de_efuse_update_chip_version()
1684 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); in _rtl92de_efuse_update_chip_version()
1688 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); in _rtl92de_efuse_update_chip_version()
1692 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); in _rtl92de_efuse_update_chip_version()
1699 rtlpriv->rtlhal.version = chipver; in _rtl92de_efuse_update_chip_version()
1704 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_adapter_info() local
1719 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) in _rtl92de_read_adapter_info()
1732 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, in _rtl92de_read_adapter_info()
1734 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); in _rtl92de_read_adapter_info()
1759 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_read_eeprom_info() local
1765 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); in rtl92de_read_eeprom_info()
1768 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); in rtl92de_read_eeprom_info()
1771 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); in rtl92de_read_eeprom_info()
1775 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); in rtl92de_read_eeprom_info()
1788 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_hal_rate_table() local
1789 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92de_update_hal_rate_table()
1862 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); in rtl92de_update_hal_rate_table()
1863 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", in rtl92de_update_hal_rate_table()
1864 rtl_read_dword(rtlpriv, REG_ARFR0)); in rtl92de_update_hal_rate_table()
1870 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_hal_rate_mask() local
1871 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92de_update_hal_rate_mask()
1995 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, in rtl92de_update_hal_rate_mask()
2006 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_hal_rate_tbl() local
2008 if (rtlpriv->dm.useramask) in rtl92de_update_hal_rate_tbl()
2016 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_channel_access_setting() local
2020 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, in rtl92de_update_channel_access_setting()
2026 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); in rtl92de_update_channel_access_setting()
2031 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_gpio_radio_on_off_checking() local
2043 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2045 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2049 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2051 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, in rtl92de_gpio_radio_on_off_checking()
2053 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); in rtl92de_gpio_radio_on_off_checking()
2056 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, in rtl92de_gpio_radio_on_off_checking()
2062 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, in rtl92de_gpio_radio_on_off_checking()
2069 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2071 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2075 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2077 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2087 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_key() local
2107 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); in rtl92de_set_key()
2113 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92de_set_key()
2115 rtlpriv->sec.key_len[idx] = 0; in rtl92de_set_key()
2138 if (is_wepkey || rtlpriv->sec.use_defaultkey) { in rtl92de_set_key()
2160 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92de_set_key()
2161 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2168 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_set_key()
2170 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); in rtl92de_set_key()
2171 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_set_key()
2173 rtlpriv->sec.key_buf[0][0], in rtl92de_set_key()
2174 rtlpriv->sec.key_buf[0][1]); in rtl92de_set_key()
2175 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2178 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_set_key()
2180 rtlpriv->sec.pairwise_key, in rtl92de_set_key()
2181 rtlpriv-> in rtl92de_set_key()
2183 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2188 rtlpriv-> in rtl92de_set_key()
2191 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2199 rtlpriv->sec.key_buf[entry_id]); in rtl92de_set_key()
2204 rtlpriv->sec.key_buf in rtl92de_set_key()
2213 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_suspend() local
2215 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv, in rtl92de_suspend()
2221 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_resume() local
2223 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL, in rtl92de_resume()
2224 rtlpriv->rtlhal.macphyctl_reg); in rtl92de_resume()