Lines Matching +full:0 +full:x349
25 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); in rtl92de_read_dword_dbi()
37 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); in rtl92de_write_dword_dbi()
39 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); in rtl92de_write_dword_dbi()
60 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in _rtl92de_stop_tx_beacon()
61 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92de_stop_tx_beacon()
63 tmp1byte &= ~(BIT(0)); in _rtl92de_stop_tx_beacon()
74 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in _rtl92de_resume_tx_beacon()
75 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92de_resume_tx_beacon()
77 tmp1byte |= BIT(0); in _rtl92de_resume_tx_beacon()
83 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92de_enable_bcn_sub_func()
88 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92de_disable_bcn_sub_func()
114 val_rcr &= 0x00070000; in rtl92de_get_hw_reg()
161 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92de_set_hw_reg()
167 u16 rate_cfg = ((u16 *) val)[0]; in rtl92de_set_hw_reg()
168 u8 rate_index = 0; in rtl92de_set_hw_reg()
170 rate_cfg = rate_cfg & 0x15f; in rtl92de_set_hw_reg()
172 ((rate_cfg & 0x150) == 0)) in rtl92de_set_hw_reg()
173 rate_cfg |= 0x01; in rtl92de_set_hw_reg()
174 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); in rtl92de_set_hw_reg()
176 (rate_cfg >> 8) & 0xff); in rtl92de_set_hw_reg()
177 while (rate_cfg > 0x1) { in rtl92de_set_hw_reg()
181 if (rtlhal->fw_version > 0xe) in rtl92de_set_hw_reg()
187 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92de_set_hw_reg()
193 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); in rtl92de_set_hw_reg()
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); in rtl92de_set_hw_reg()
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); in rtl92de_set_hw_reg()
199 0x0e0e); in rtl92de_set_hw_reg()
208 "HW_VAR_SLOT_TIME %x\n", val[0]); in rtl92de_set_hw_reg()
209 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); in rtl92de_set_hw_reg()
210 for (e_aci = 0; e_aci < AC_MAX; e_aci++) in rtl92de_set_hw_reg()
222 reg_tmp |= 0x80; in rtl92de_set_hw_reg()
232 sec_min_space = 0; in rtl92de_set_hw_reg()
235 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | in rtl92de_set_hw_reg()
266 regtoset = 0xb9726641; in rtl92de_set_hw_reg()
268 regtoset = 0x66626641; in rtl92de_set_hw_reg()
270 regtoset = 0xb972a841; in rtl92de_set_hw_reg()
274 if (factor_toset > 0xf) in rtl92de_set_hw_reg()
275 factor_toset = 0xf; in rtl92de_set_hw_reg()
276 for (index = 0; index < 4; index++) { in rtl92de_set_hw_reg()
278 if ((*ptmp_byte & 0xf0) > in rtl92de_set_hw_reg()
280 *ptmp_byte = (*ptmp_byte & 0x0f) in rtl92de_set_hw_reg()
282 if ((*ptmp_byte & 0x0f) > factor_toset) in rtl92de_set_hw_reg()
283 *ptmp_byte = (*ptmp_byte & 0xf0) in rtl92de_set_hw_reg()
304 (union aci_aifsn *)(&(mac->ac[0].aifs)); in rtl92de_set_hw_reg()
308 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92de_set_hw_reg()
344 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", in rtl92de_set_hw_reg()
350 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92de_set_hw_reg()
351 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92de_set_hw_reg()
354 u8 retry_limit = val[0]; in rtl92de_set_hw_reg()
362 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); in rtl92de_set_hw_reg()
394 (tmp_regcr | BIT(0))); in rtl92de_set_hw_reg()
395 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92de_set_hw_reg()
396 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92de_set_hw_reg()
403 rtl92d_set_fw_rsvdpagepkt(hw, 0); in rtl92de_set_hw_reg()
404 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92de_set_hw_reg()
405 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92de_set_hw_reg()
411 (tmp_regcr & ~(BIT(0)))); in rtl92de_set_hw_reg()
419 u2btmp &= 0xC000; in rtl92de_set_hw_reg()
425 u8 btype_ibss = val[0]; in rtl92de_set_hw_reg()
429 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92de_set_hw_reg()
431 (u32) (mac->tsf & 0xffffffff)); in rtl92de_set_hw_reg()
433 (u32) ((mac->tsf >> 32) & 0xffffffff)); in rtl92de_set_hw_reg()
434 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92de_set_hw_reg()
446 * timer 25ns*0xfa0=100us for 0xf packets. in rtl92de_set_hw_reg()
447 * 0x306:Rx, 0x307:Tx */ in rtl92de_set_hw_reg()
448 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0); in rtl92de_set_hw_reg()
452 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in rtl92de_set_hw_reg()
467 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, in rtl92de_set_hw_reg()
473 RT_AC_INT_MASKS, 0); in rtl92de_set_hw_reg()
488 long count = 0; in _rtl92de_llt_write()
520 value8 = 0; in _rtl92de_llt_table_init()
521 value32 = 0x80bf0d29; in _rtl92de_llt_table_init()
525 value8 = 0; in _rtl92de_llt_table_init()
526 value32 = 0x80750005; in _rtl92de_llt_table_init()
530 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */ in _rtl92de_llt_table_init()
535 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */ in _rtl92de_llt_table_init()
541 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */ in _rtl92de_llt_table_init()
545 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */ in _rtl92de_llt_table_init()
550 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */ in _rtl92de_llt_table_init()
552 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); in _rtl92de_llt_table_init()
556 /* 16. PBP [7:0] = 0x11 */ in _rtl92de_llt_table_init()
558 rtl_write_byte(rtlpriv, REG_PBP, 0x11); in _rtl92de_llt_table_init()
560 /* 17. DRV_INFO_SZ = 0x04 */ in _rtl92de_llt_table_init()
561 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); in _rtl92de_llt_table_init()
564 for (i = 0; i < (txpktbuf_bndy - 1); i++) { in _rtl92de_llt_table_init()
571 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); in _rtl92de_llt_table_init()
621 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */ in _rtl92de_init_mac()
623 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); in _rtl92de_init_mac()
624 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05); in _rtl92de_init_mac()
626 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */ in _rtl92de_init_mac()
627 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */ in _rtl92de_init_mac()
631 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */ in _rtl92de_init_mac()
632 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92de_init_mac()
634 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */ in _rtl92de_init_mac()
635 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); in _rtl92de_init_mac()
640 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */ in _rtl92de_init_mac()
642 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); in _rtl92de_init_mac()
647 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */ in _rtl92de_init_mac()
650 retry = 0; in _rtl92de_init_mac()
651 while ((bytetmp & BIT(0)) && retry < 1000) { in _rtl92de_init_mac()
658 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */ in _rtl92de_init_mac()
659 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); in _rtl92de_init_mac()
662 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */ in _rtl92de_init_mac()
663 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */ in _rtl92de_init_mac()
664 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); in _rtl92de_init_mac()
668 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */ in _rtl92de_init_mac()
671 rtl_write_word(rtlpriv, REG_CR, 0x0); in _rtl92de_init_mac()
674 rtl_write_word(rtlpriv, REG_CR, 0x2ff); in _rtl92de_init_mac()
677 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0); in _rtl92de_init_mac()
679 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */ in _rtl92de_init_mac()
687 /* 19. HISR 0x124[31:0] = 0xffffffff; */ in _rtl92de_init_mac()
688 /* HISRE 0x12C[7:0] = 0xFF */ in _rtl92de_init_mac()
689 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); in _rtl92de_init_mac()
690 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); in _rtl92de_init_mac()
692 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */ in _rtl92de_init_mac()
693 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */ in _rtl92de_init_mac()
698 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */ in _rtl92de_init_mac()
709 wordtmp &= 0xf; in _rtl92de_init_mac()
710 wordtmp |= 0xF771; in _rtl92de_init_mac()
716 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); in _rtl92de_init_mac()
720 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */ in _rtl92de_init_mac()
730 rtl_write_byte(rtlpriv, 0x4d0, 0x0); in _rtl92de_init_mac()
748 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33); in _rtl92de_init_mac()
751 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in _rtl92de_init_mac()
765 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); in _rtl92de_init_mac()
779 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); in _rtl92de_hw_configure()
782 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in _rtl92de_hw_configure()
783 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); in _rtl92de_hw_configure()
784 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); in _rtl92de_hw_configure()
785 rtl_write_word(rtlpriv, REG_RL, 0x0707); in _rtl92de_hw_configure()
786 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); in _rtl92de_hw_configure()
787 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); in _rtl92de_hw_configure()
788 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); in _rtl92de_hw_configure()
789 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
790 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); in _rtl92de_hw_configure()
791 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
794 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641); in _rtl92de_hw_configure()
796 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641); in _rtl92de_hw_configure()
798 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); in _rtl92de_hw_configure()
799 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); in _rtl92de_hw_configure()
800 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in _rtl92de_hw_configure()
801 rtlpci->reg_bcn_ctrl_val = 0x1f; in _rtl92de_hw_configure()
803 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92de_hw_configure()
804 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); in _rtl92de_hw_configure()
805 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); in _rtl92de_hw_configure()
806 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); in _rtl92de_hw_configure()
808 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666); in _rtl92de_hw_configure()
810 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); in _rtl92de_hw_configure()
812 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
813 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
815 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); in _rtl92de_hw_configure()
817 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); in _rtl92de_hw_configure()
819 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); in _rtl92de_hw_configure()
820 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); in _rtl92de_hw_configure()
838 rtl_write_byte(rtlpriv, 0x34b, 0x93); in _rtl92de_enable_aspm_back_door()
839 rtl_write_word(rtlpriv, 0x350, 0x870c); in _rtl92de_enable_aspm_back_door()
840 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
842 rtl_write_byte(rtlpriv, 0x349, 0x1b); in _rtl92de_enable_aspm_back_door()
844 rtl_write_byte(rtlpriv, 0x349, 0x03); in _rtl92de_enable_aspm_back_door()
845 rtl_write_word(rtlpriv, 0x350, 0x2718); in _rtl92de_enable_aspm_back_door()
846 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
869 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); in rtl92de_enable_hw_security_config()
909 rtlhal->last_hmeboxnum = 0; in rtl92de_hw_init()
912 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
913 tmp_u1b = tmp_u1b | 0x30; in rtl92de_hw_init()
914 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
920 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0); in rtl92de_hw_init()
921 tmp_u1b = tmp_u1b | 0x1f; in rtl92de_hw_init()
922 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b); in rtl92de_hw_init()
924 rtl_write_byte(rtlpriv, 0x4d3, 0x80); in rtl92de_hw_init()
926 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
927 tmp_u1b = tmp_u1b | 0x40; in rtl92de_hw_init()
928 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
932 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); in rtl92de_hw_init()
933 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); in rtl92de_hw_init()
934 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); in rtl92de_hw_init()
949 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in rtl92de_hw_init()
959 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in rtl92de_hw_init()
960 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, in rtl92de_hw_init()
967 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92de_hw_init()
968 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92de_hw_init()
969 if (rtlhal->interfaceindex == 0) { in rtl92de_hw_init()
1006 for (i = 0; i < 10000; i++) { in rtl92de_hw_init()
1011 0x2a, MASKDWORD); in rtl92de_hw_init()
1034 if (!(value32 & 0x000f0000)) { in _rtl92de_read_chip_version()
1051 bt_msr &= 0xfc; in _rtl92de_set_media_status()
1096 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92de_set_media_status()
1098 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92de_set_media_status()
1099 return 0; in _rtl92de_set_media_status()
1115 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92de_set_check_bssid()
1118 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92de_set_check_bssid()
1137 return 0; in rtl92de_set_network_type()
1171 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
1172 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
1193 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); in _rtl92de_poweroff_adapter()
1194 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0); in _rtl92de_poweroff_adapter()
1195 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0); in _rtl92de_poweroff_adapter()
1197 /* 0x20:value 05-->04 */ in _rtl92de_poweroff_adapter()
1198 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); in _rtl92de_poweroff_adapter()
1203 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */ in _rtl92de_poweroff_adapter()
1204 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); in _rtl92de_poweroff_adapter()
1206 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */ in _rtl92de_poweroff_adapter()
1207 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in _rtl92de_poweroff_adapter()
1211 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */ in _rtl92de_poweroff_adapter()
1212 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); in _rtl92de_poweroff_adapter()
1214 /* i. Value = GPIO_PIN_CTRL[7:0] */ in _rtl92de_poweroff_adapter()
1217 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */ in _rtl92de_poweroff_adapter()
1220 0x00FF0000 | (u1b_tmp << 8)); in _rtl92de_poweroff_adapter()
1222 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */ in _rtl92de_poweroff_adapter()
1223 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); in _rtl92de_poweroff_adapter()
1225 /* l. LEDCFG 0x4C[15:0] = 0x8080 */ in _rtl92de_poweroff_adapter()
1226 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); in _rtl92de_poweroff_adapter()
1230 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */ in _rtl92de_poweroff_adapter()
1231 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); in _rtl92de_poweroff_adapter()
1233 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */ in _rtl92de_poweroff_adapter()
1234 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); in _rtl92de_poweroff_adapter()
1236 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */ in _rtl92de_poweroff_adapter()
1237 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
1239 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */ in _rtl92de_poweroff_adapter()
1240 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
1244 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */ in _rtl92de_poweroff_adapter()
1246 /* value as 0x18. Otherwise, we may not L0s sometimes. */ in _rtl92de_poweroff_adapter()
1248 /* set as 0x00 do not affect power current. And if it */ in _rtl92de_poweroff_adapter()
1249 /* is set as 0x18, they had ever met auto load fail problem. */ in _rtl92de_poweroff_adapter()
1250 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); in _rtl92de_poweroff_adapter()
1258 /* 0x17[7] 1b': power off in process 0b' : power off over */ in _rtl92de_poweroff_adapter()
1294 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); in rtl92de_card_disable()
1297 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ in rtl92de_card_disable()
1300 /* 0x88c[23:20] = 0xf. */ in rtl92de_card_disable()
1301 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in rtl92de_card_disable()
1302 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in rtl92de_card_disable()
1304 /* APSD_CTRL 0x600[7:0] = 0x40 */ in rtl92de_card_disable()
1305 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in rtl92de_card_disable()
1307 /* Close antenna 0,0xc04,0xd04 */ in rtl92de_card_disable()
1308 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0); in rtl92de_card_disable()
1309 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0); in rtl92de_card_disable()
1311 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */ in rtl92de_card_disable()
1312 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92de_card_disable()
1315 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */ in rtl92de_card_disable()
1317 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); in rtl92de_card_disable()
1320 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */ in rtl92de_card_disable()
1322 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); in rtl92de_card_disable()
1324 rtl_write_byte(rtlpriv, REG_CR, 0x0); in rtl92de_card_disable()
1337 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92de_interrupt_recognized()
1352 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); in rtl92de_set_beacon_related_registers()
1353 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); in rtl92de_set_beacon_related_registers()
1355 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); in rtl92de_set_beacon_related_registers()
1357 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); in rtl92de_set_beacon_related_registers()
1358 rtl_write_byte(rtlpriv, 0x606, 0x30); in rtl92de_set_beacon_related_registers()
1383 rtlpci->irq_mask[0] |= add_msr; in rtl92de_update_interrupt_mask()
1385 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92de_update_interrupt_mask()
1396 memset(pwrinfo, 0, sizeof(struct txpower_info)); in _rtl92de_readpowervalue_fromprom()
1398 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { in _rtl92de_readpowervalue_fromprom()
1399 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { in _rtl92de_readpowervalue_fromprom()
1421 for (i = 0; i < 3; i++) { in _rtl92de_readpowervalue_fromprom()
1430 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { in _rtl92de_readpowervalue_fromprom()
1431 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { in _rtl92de_readpowervalue_fromprom()
1435 (rom_content[eeaddr] == 0xFF) ? in _rtl92de_readpowervalue_fromprom()
1436 (eeaddr > 0x7B ? in _rtl92de_readpowervalue_fromprom()
1442 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { in _rtl92de_readpowervalue_fromprom()
1443 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { in _rtl92de_readpowervalue_fromprom()
1449 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? in _rtl92de_readpowervalue_fromprom()
1456 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { in _rtl92de_readpowervalue_fromprom()
1457 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { in _rtl92de_readpowervalue_fromprom()
1463 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) in _rtl92de_readpowervalue_fromprom()
1467 & 0xF; in _rtl92de_readpowervalue_fromprom()
1472 + offset1 * 21] != 0xFF) in _rtl92de_readpowervalue_fromprom()
1476 & 0xF; in _rtl92de_readpowervalue_fromprom()
1481 + offset1 * 21] != 0xFF) in _rtl92de_readpowervalue_fromprom()
1485 & 0xF; in _rtl92de_readpowervalue_fromprom()
1490 + offset1 * 21] != 0xFF) in _rtl92de_readpowervalue_fromprom()
1494 & 0xF; in _rtl92de_readpowervalue_fromprom()
1499 + offset1 * 21] != 0xFF) in _rtl92de_readpowervalue_fromprom()
1503 0xF; in _rtl92de_readpowervalue_fromprom()
1509 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { in _rtl92de_readpowervalue_fromprom()
1511 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; in _rtl92de_readpowervalue_fromprom()
1512 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; in _rtl92de_readpowervalue_fromprom()
1514 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; in _rtl92de_readpowervalue_fromprom()
1516 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | in _rtl92de_readpowervalue_fromprom()
1517 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; in _rtl92de_readpowervalue_fromprom()
1520 0xF0) >> 4 | in _rtl92de_readpowervalue_fromprom()
1521 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; in _rtl92de_readpowervalue_fromprom()
1523 0xFC) >> 2; in _rtl92de_readpowervalue_fromprom()
1525 for (i = 0; i < 3; i++) { in _rtl92de_readpowervalue_fromprom()
1544 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); in _rtl92de_read_txpower_info()
1546 hwinfo[EEPROM_THERMAL_METER] & 0x1f; in _rtl92de_read_txpower_info()
1548 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; in _rtl92de_read_txpower_info()
1549 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; in _rtl92de_read_txpower_info()
1553 rtlefuse->internal_pa_5g[0] = in _rtl92de_read_txpower_info()
1559 rtlefuse->internal_pa_5g[0], in _rtl92de_read_txpower_info()
1565 rtlefuse->eeprom_regulatory = 0; in _rtl92de_read_txpower_info()
1568 tempval[0] = tempval[1] = 3; in _rtl92de_read_txpower_info()
1575 if (rtlefuse->eeprom_thermalmeter < 0x06 || in _rtl92de_read_txpower_info()
1576 rtlefuse->eeprom_thermalmeter > 0x1c) in _rtl92de_read_txpower_info()
1577 rtlefuse->eeprom_thermalmeter = 0x12; in _rtl92de_read_txpower_info()
1578 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; in _rtl92de_read_txpower_info()
1581 if (rtlefuse->crystalcap == 0xFF) in _rtl92de_read_txpower_info()
1582 rtlefuse->crystalcap = 0; in _rtl92de_read_txpower_info()
1584 rtlefuse->eeprom_regulatory = 0; in _rtl92de_read_txpower_info()
1586 for (i = 0; i < 2; i++) { in _rtl92de_read_txpower_info()
1588 case 0: in _rtl92de_read_txpower_info()
1599 tempval[i] = 0; in _rtl92de_read_txpower_info()
1604 rtlefuse->delta_iqk = tempval[0]; in _rtl92de_read_txpower_info()
1605 if (tempval[1] > 0) in _rtl92de_read_txpower_info()
1607 if (rtlefuse->eeprom_c9 == 0xFF) in _rtl92de_read_txpower_info()
1608 rtlefuse->eeprom_c9 = 0x00; in _rtl92de_read_txpower_info()
1610 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory); in _rtl92de_read_txpower_info()
1612 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); in _rtl92de_read_txpower_info()
1614 "CrystalCap = 0x%x\n", rtlefuse->crystalcap); in _rtl92de_read_txpower_info()
1616 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n", in _rtl92de_read_txpower_info()
1619 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { in _rtl92de_read_txpower_info()
1620 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { in _rtl92de_read_txpower_info()
1638 (pwr > diff) ? (pwr - diff) : 0; in _rtl92de_read_txpower_info()
1679 &cutvalue[0]); in _rtl92de_efuse_update_chip_version()
1680 chipvalue = (cutvalue[1] << 8) | cutvalue[0]; in _rtl92de_efuse_update_chip_version()
1682 case 0xAA55: in _rtl92de_efuse_update_chip_version()
1686 case 0x9966: in _rtl92de_efuse_update_chip_version()
1690 case 0xCC33: in _rtl92de_efuse_update_chip_version()
1726 if (rtlhal->interfaceindex != 0) { in _rtl92de_read_adapter_info()
1727 for (i = 0; i < 6; i += 2) { in _rtl92de_read_adapter_info()
1793 u8 ratr_index = 0; in rtl92de_update_hal_rate_table()
1800 1 : 0; in rtl92de_update_hal_rate_table()
1802 1 : 0; in rtl92de_update_hal_rate_table()
1808 ratr_value = sta->deflink.supp_rates[0]; in rtl92de_update_hal_rate_table()
1810 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92de_update_hal_rate_table()
1813 ratr_value &= 0x00000FF0; in rtl92de_update_hal_rate_table()
1816 if (ratr_value & 0x0000000c) in rtl92de_update_hal_rate_table()
1817 ratr_value &= 0x0000000d; in rtl92de_update_hal_rate_table()
1819 ratr_value &= 0x0000000f; in rtl92de_update_hal_rate_table()
1822 ratr_value &= 0x00000FF5; in rtl92de_update_hal_rate_table()
1828 ratr_value &= 0x0007F005; in rtl92de_update_hal_rate_table()
1834 ratr_mask = 0x000ff005; in rtl92de_update_hal_rate_table()
1836 ratr_mask = 0x0f0ff005; in rtl92de_update_hal_rate_table()
1844 ratr_value &= 0x000ff0ff; in rtl92de_update_hal_rate_table()
1846 ratr_value &= 0x0f0ff0ff; in rtl92de_update_hal_rate_table()
1850 ratr_value &= 0x0FFFFFFF; in rtl92de_update_hal_rate_table()
1853 ratr_value |= 0x10000000; in rtl92de_update_hal_rate_table()
1855 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { in rtl92de_update_hal_rate_table()
1877 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; in rtl92de_update_hal_rate_mask()
1879 1 : 0; in rtl92de_update_hal_rate_mask()
1881 1 : 0; in rtl92de_update_hal_rate_mask()
1882 enum wireless_mode wirelessmode = 0; in rtl92de_update_hal_rate_mask()
1885 u8 macid = 0; in rtl92de_update_hal_rate_mask()
1900 ratr_bitmap = sta->deflink.supp_rates[0]; in rtl92de_update_hal_rate_mask()
1902 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92de_update_hal_rate_mask()
1906 if (ratr_bitmap & 0x0000000c) in rtl92de_update_hal_rate_mask()
1907 ratr_bitmap &= 0x0000000d; in rtl92de_update_hal_rate_mask()
1909 ratr_bitmap &= 0x0000000f; in rtl92de_update_hal_rate_mask()
1915 ratr_bitmap &= 0x00000f00; in rtl92de_update_hal_rate_mask()
1917 ratr_bitmap &= 0x00000ff0; in rtl92de_update_hal_rate_mask()
1919 ratr_bitmap &= 0x00000ff5; in rtl92de_update_hal_rate_mask()
1923 ratr_bitmap &= 0x00000ff0; in rtl92de_update_hal_rate_mask()
1933 ratr_bitmap &= 0x00070000; in rtl92de_update_hal_rate_mask()
1935 ratr_bitmap &= 0x0007f000; in rtl92de_update_hal_rate_mask()
1937 ratr_bitmap &= 0x0007f005; in rtl92de_update_hal_rate_mask()
1943 ratr_bitmap &= 0x000f0000; in rtl92de_update_hal_rate_mask()
1945 ratr_bitmap &= 0x000ff000; in rtl92de_update_hal_rate_mask()
1947 ratr_bitmap &= 0x000ff015; in rtl92de_update_hal_rate_mask()
1950 ratr_bitmap &= 0x000f0000; in rtl92de_update_hal_rate_mask()
1952 ratr_bitmap &= 0x000ff000; in rtl92de_update_hal_rate_mask()
1954 ratr_bitmap &= 0x000ff005; in rtl92de_update_hal_rate_mask()
1959 ratr_bitmap &= 0x0f0f0000; in rtl92de_update_hal_rate_mask()
1961 ratr_bitmap &= 0x0f0ff000; in rtl92de_update_hal_rate_mask()
1963 ratr_bitmap &= 0x0f0ff015; in rtl92de_update_hal_rate_mask()
1966 ratr_bitmap &= 0x0f0f0000; in rtl92de_update_hal_rate_mask()
1968 ratr_bitmap &= 0x0f0ff000; in rtl92de_update_hal_rate_mask()
1970 ratr_bitmap &= 0x0f0ff005; in rtl92de_update_hal_rate_mask()
1977 if (macid == 0) in rtl92de_update_hal_rate_mask()
1987 ratr_bitmap &= 0x000ff0ff; in rtl92de_update_hal_rate_mask()
1989 ratr_bitmap &= 0x0f0ff0ff; in rtl92de_update_hal_rate_mask()
1993 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); in rtl92de_update_hal_rate_mask()
1994 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; in rtl92de_update_hal_rate_mask()
1997 ratr_bitmap, value[0], value[1]); in rtl92de_update_hal_rate_mask()
1999 if (macid != 0) in rtl92de_update_hal_rate_mask()
2023 sifs_timer = 0x0a0a; in rtl92de_update_channel_access_setting()
2025 sifs_timer = 0x1010; in rtl92de_update_channel_access_setting()
2094 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, in rtl92de_set_key()
2095 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, in rtl92de_set_key()
2096 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, in rtl92de_set_key()
2097 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} in rtl92de_set_key()
2100 0xff, 0xff, 0xff, 0xff, 0xff, 0xff in rtl92de_set_key()
2105 u8 cam_offset = 0; in rtl92de_set_key()
2108 for (idx = 0; idx < clear_number; idx++) { in rtl92de_set_key()
2113 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92de_set_key()
2115 rtlpriv->sec.key_len[idx] = 0; in rtl92de_set_key()
2160 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92de_set_key()
2173 rtlpriv->sec.key_buf[0][0], in rtl92de_set_key()
2174 rtlpriv->sec.key_buf[0][1]); in rtl92de_set_key()