Lines Matching refs:PWR_BASEADDR_MAC
46 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
49 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0 \
52 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
55 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0 \
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0) \
64 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0 \
67 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
75 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
78 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
81 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
84 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0 \
90 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3) \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4) \
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7) \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
122 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
131 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) \
135 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
139 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
142 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
159 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \
164 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/}, \
166 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
171 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
175 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
178 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
181 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
184 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
187 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
190 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0 \
193 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
196 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F \
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0 \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5) \
211 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
214 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
217 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
220 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
223 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0 \
226 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0 \
229 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
232 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
235 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0) \
238 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \