Lines Matching refs:val32
310 u32 val32, sys_cfg, vendor; in rtl8723bu_identify_chip() local
327 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8723bu_identify_chip()
328 if (val32 & MULTI_WIFI_FUNC_EN) in rtl8723bu_identify_chip()
330 if (val32 & MULTI_BT_FUNC_EN) in rtl8723bu_identify_chip()
332 if (val32 & MULTI_GPS_FUNC_EN) in rtl8723bu_identify_chip()
339 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8723bu_identify_chip()
340 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8723bu_identify_chip()
407 u32 val32, ofdm, mcs; in rtl8723b_set_tx_power() local
415 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723b_set_tx_power()
416 val32 &= 0xffff00ff; in rtl8723b_set_tx_power()
417 val32 |= (cck << 8); in rtl8723b_set_tx_power()
418 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
420 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723b_set_tx_power()
421 val32 &= 0xff; in rtl8723b_set_tx_power()
422 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8723b_set_tx_power()
423 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
555 u32 val32; in rtl8723bu_phy_init_antenna_selection() local
557 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); in rtl8723bu_phy_init_antenna_selection()
558 val32 &= ~(BIT(20) | BIT(24)); in rtl8723bu_phy_init_antenna_selection()
559 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
561 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
562 val32 &= ~BIT(4); in rtl8723bu_phy_init_antenna_selection()
563 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
565 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
566 val32 |= BIT(3); in rtl8723bu_phy_init_antenna_selection()
567 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
569 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
570 val32 |= BIT(24); in rtl8723bu_phy_init_antenna_selection()
571 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
573 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
574 val32 &= ~BIT(23); in rtl8723bu_phy_init_antenna_selection()
575 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
577 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723bu_phy_init_antenna_selection()
578 val32 |= (BIT(0) | BIT(1)); in rtl8723bu_phy_init_antenna_selection()
579 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723bu_phy_init_antenna_selection()
581 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); in rtl8723bu_phy_init_antenna_selection()
582 val32 &= 0xffffff00; in rtl8723bu_phy_init_antenna_selection()
583 val32 |= 0x77; in rtl8723bu_phy_init_antenna_selection()
584 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); in rtl8723bu_phy_init_antenna_selection()
586 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723bu_phy_init_antenna_selection()
587 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; in rtl8723bu_phy_init_antenna_selection()
588 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723bu_phy_init_antenna_selection()
593 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; in rtl8723bu_iqk_path_a() local
601 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
602 val32 &= 0x000000ff; in rtl8723bu_iqk_path_a()
603 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
608 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_iqk_path_a()
609 val32 |= 0x80000; in rtl8723bu_iqk_path_a()
610 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_iqk_path_a()
638 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
639 val32 &= 0x000000ff; in rtl8723bu_iqk_path_a()
640 val32 |= 0x80800000; in rtl8723bu_iqk_path_a()
641 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
674 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
675 val32 &= 0x000000ff; in rtl8723bu_iqk_path_a()
676 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
683 val32 = (reg_e9c >> 16) & 0x3ff; in rtl8723bu_iqk_path_a()
684 if (val32 & 0x200) in rtl8723bu_iqk_path_a()
685 val32 = 0x400 - val32; in rtl8723bu_iqk_path_a()
692 val32 < 0xf) in rtl8723bu_iqk_path_a()
703 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; in rtl8723bu_rx_iqk_path_a() local
711 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
712 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
713 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
718 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
719 val32 |= 0x80000; in rtl8723bu_rx_iqk_path_a()
720 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
748 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
749 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
750 val32 |= 0x80800000; in rtl8723bu_rx_iqk_path_a()
751 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
784 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
785 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
786 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
793 val32 = (reg_e9c >> 16) & 0x3ff; in rtl8723bu_rx_iqk_path_a()
794 if (val32 & 0x200) in rtl8723bu_rx_iqk_path_a()
795 val32 = 0x400 - val32; in rtl8723bu_rx_iqk_path_a()
802 val32 < 0xf) in rtl8723bu_rx_iqk_path_a()
807 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | in rtl8723bu_rx_iqk_path_a()
809 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8723bu_rx_iqk_path_a()
814 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
815 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
816 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
817 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
818 val32 |= 0x80000; in rtl8723bu_rx_iqk_path_a()
819 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
852 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
853 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
854 val32 |= 0x80800000; in rtl8723bu_rx_iqk_path_a()
855 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
883 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
884 val32 &= 0x000000ff; in rtl8723bu_rx_iqk_path_a()
885 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
893 val32 = (reg_eac >> 16) & 0x3ff; in rtl8723bu_rx_iqk_path_a()
894 if (val32 & 0x200) in rtl8723bu_rx_iqk_path_a()
895 val32 = 0x400 - val32; in rtl8723bu_rx_iqk_path_a()
902 val32 < 0xf) in rtl8723bu_rx_iqk_path_a()
914 u32 i, val32; in rtl8723bu_phy_iqcalibrate() local
959 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8723bu_phy_iqcalibrate()
960 val32 |= 0x0f000000; in rtl8723bu_phy_iqcalibrate()
961 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8723bu_phy_iqcalibrate()
971 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
972 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
973 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
975 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iqcalibrate()
976 val32 |= 0x80000; in rtl8723bu_phy_iqcalibrate()
977 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iqcalibrate()
983 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iqcalibrate()
984 val32 |= 0x20; in rtl8723bu_phy_iqcalibrate()
985 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iqcalibrate()
992 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
993 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
994 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
996 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
998 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
999 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1001 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1013 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1015 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1016 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1018 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1035 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1036 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
1037 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1040 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1041 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
1042 val32 |= 0x80800000; in rtl8723bu_phy_iqcalibrate()
1043 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1051 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8723bu_phy_iqcalibrate()
1052 result[t][4] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1053 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8723bu_phy_iqcalibrate()
1054 result[t][5] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1065 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1067 result[t][6] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1068 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1070 result[t][7] = (val32 >> 16) & 0x3ff; in rtl8723bu_phy_iqcalibrate()
1081 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1082 val32 &= 0x000000ff; in rtl8723bu_phy_iqcalibrate()
1083 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1098 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1099 val32 &= 0xffffff00; in rtl8723bu_phy_iqcalibrate()
1100 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1101 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8723bu_phy_iqcalibrate()
1104 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1105 val32 &= 0xffffff00; in rtl8723bu_phy_iqcalibrate()
1107 val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1109 val32 | xb_agc); in rtl8723bu_phy_iqcalibrate()
1126 u32 val32, bt_control; in rtl8723bu_phy_iq_calibrate() local
1225 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iq_calibrate()
1226 val32 |= 0x80000; in rtl8723bu_phy_iq_calibrate()
1227 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iq_calibrate()
1231 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iq_calibrate()
1232 val32 |= 0x20; in rtl8723bu_phy_iq_calibrate()
1233 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iq_calibrate()
1246 u32 val32; in rtl8723bu_active_to_emu() local
1258 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723bu_active_to_emu()
1259 val32 |= APS_FSMCO_WLON_RESET; in rtl8723bu_active_to_emu()
1260 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723bu_active_to_emu()
1303 u32 val32; in rtl8723b_emu_to_active() local
1324 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1325 val32 &= ~APS_FSMCO_SW_LPS; in rtl8723b_emu_to_active()
1326 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1330 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1331 if (val32 & BIT(17)) in rtl8723b_emu_to_active()
1345 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1346 val32 |= APS_FSMCO_WLON_RESET; in rtl8723b_emu_to_active()
1347 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1350 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1351 val32 &= ~APS_FSMCO_HW_POWERDOWN; in rtl8723b_emu_to_active()
1352 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1355 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1356 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); in rtl8723b_emu_to_active()
1357 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1360 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1361 val32 |= APS_FSMCO_MAC_ENABLE; in rtl8723b_emu_to_active()
1362 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1365 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1366 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8723b_emu_to_active()
1425 u32 val32; in rtl8723bu_power_on() local
1466 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_power_on()
1467 val32 |= LEDCFG0_DPDT_SELECT; in rtl8723bu_power_on()
1468 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_power_on()
1522 u32 val32; in rtl8723b_enable_rf() local
1525 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8723b_enable_rf()
1526 val32 |= (BIT(22) | BIT(23)); in rtl8723b_enable_rf()
1527 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8723b_enable_rf()
1569 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723b_enable_rf()
1570 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; in rtl8723b_enable_rf()
1571 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723b_enable_rf()
1578 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723b_enable_rf()
1579 val32 |= (BIT(0) | BIT(1)); in rtl8723b_enable_rf()
1580 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723b_enable_rf()
1584 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723b_enable_rf()
1585 val32 &= ~BIT(24); in rtl8723b_enable_rf()
1586 val32 |= BIT(23); in rtl8723b_enable_rf()
1587 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723b_enable_rf()
1654 u32 val32; in rtl8723bu_init_statistics() local
1662 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_init_statistics()
1663 val32 |= 0xff; in rtl8723bu_init_statistics()
1664 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_init_statistics()
1666 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8723bu_init_statistics()
1667 val32 |= BIT(8) | BIT(9) | BIT(10); in rtl8723bu_init_statistics()
1668 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8723bu_init_statistics()
1670 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8723bu_init_statistics()
1671 val32 |= BIT(7); in rtl8723bu_init_statistics()
1672 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8723bu_init_statistics()