Lines Matching refs:val32
484 u32 val32, bonding, sys_cfg, vendor; in rtl8192eu_identify_chip() local
513 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192eu_identify_chip()
514 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192eu_identify_chip()
531 u32 val32, ofdm, mcs; in rtl8192e_set_tx_power() local
540 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
541 val32 &= 0xffff00ff; in rtl8192e_set_tx_power()
542 val32 |= (cck << 8); in rtl8192e_set_tx_power()
543 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
545 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
546 val32 &= 0xff; in rtl8192e_set_tx_power()
547 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8192e_set_tx_power()
548 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
572 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8192e_set_tx_power()
573 val32 &= 0xff; in rtl8192e_set_tx_power()
574 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8192e_set_tx_power()
575 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8192e_set_tx_power()
577 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
578 val32 &= 0xffffff00; in rtl8192e_set_tx_power()
579 val32 |= cck; in rtl8192e_set_tx_power()
580 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
761 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; in rtl8192eu_rx_iqk_path_a() local
823 val32 = 0x80007c00 | in rtl8192eu_rx_iqk_path_a()
825 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_a()
937 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; in rtl8192eu_rx_iqk_path_b() local
1002 val32 = 0x80007c00 | in rtl8192eu_rx_iqk_path_b()
1004 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_b()
1070 u32 i, val32; in rtl8192eu_phy_iqcalibrate() local
1115 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8192eu_phy_iqcalibrate()
1116 val32 |= 0x0f000000; in rtl8192eu_phy_iqcalibrate()
1117 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8192eu_phy_iqcalibrate()
1123 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8192eu_phy_iqcalibrate()
1124 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); in rtl8192eu_phy_iqcalibrate()
1125 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8192eu_phy_iqcalibrate()
1127 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1128 val32 |= BIT(10); in rtl8192eu_phy_iqcalibrate()
1129 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1130 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1131 val32 |= BIT(10); in rtl8192eu_phy_iqcalibrate()
1132 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1141 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1143 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1144 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1146 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1158 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1160 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1161 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1163 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1188 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_phy_iqcalibrate()
1189 result[t][4] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1190 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_phy_iqcalibrate()
1191 result[t][5] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1202 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1204 result[t][6] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1205 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1207 result[t][7] = (val32 >> 16) & 0x3ff; in rtl8192eu_phy_iqcalibrate()
1232 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1233 val32 &= 0xffffff00; in rtl8192eu_phy_iqcalibrate()
1234 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1235 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8192eu_phy_iqcalibrate()
1238 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1239 val32 &= 0xffffff00; in rtl8192eu_phy_iqcalibrate()
1241 val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1243 val32 | xb_agc); in rtl8192eu_phy_iqcalibrate()
1349 u32 val32; in rtl8192e_crystal_afe_adjust() local
1358 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1359 val32 &= 0xfffffc7f; in rtl8192e_crystal_afe_adjust()
1360 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1373 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1374 val32 &= 0xffdfffff; in rtl8192e_crystal_afe_adjust()
1375 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1391 u32 val32; in rtl8192e_emu_to_active() local
1411 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1412 if (val32 & BIT(17)) in rtl8192e_emu_to_active()
1431 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1432 val32 |= APS_FSMCO_MAC_ENABLE; in rtl8192e_emu_to_active()
1433 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8192e_emu_to_active()
1436 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1437 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8192e_emu_to_active()
1458 u32 val32; in rtl8192eu_active_to_lps() local
1469 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192eu_active_to_lps()
1470 if (!val32) { in rtl8192eu_active_to_lps()
1566 u32 val32; in rtl8192eu_power_on() local
1569 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_power_on()
1570 if (val32 & SYS_CFG_SPS_LDO_SEL) { in rtl8192eu_power_on()
1576 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); in rtl8192eu_power_on()
1577 val32 &= 0xff0fffff; in rtl8192eu_power_on()
1578 val32 |= 0x00500000; in rtl8192eu_power_on()
1579 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); in rtl8192eu_power_on()
1647 u32 val32; in rtl8192e_enable_rf() local
1650 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8192e_enable_rf()
1651 val32 |= (BIT(22) | BIT(23)); in rtl8192e_enable_rf()
1652 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8192e_enable_rf()
1663 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8192e_enable_rf()
1664 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; in rtl8192e_enable_rf()
1665 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8192e_enable_rf()
1667 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192e_enable_rf()
1668 val32 |= (BIT(0) | BIT(1)); in rtl8192e_enable_rf()
1669 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192e_enable_rf()
1673 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8192e_enable_rf()
1674 val32 &= ~BIT(24); in rtl8192e_enable_rf()
1675 val32 |= BIT(23); in rtl8192e_enable_rf()
1676 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8192e_enable_rf()