Lines Matching refs:val32
376 u32 val32, ofdm, mcs; in rtl8188f_set_tx_power() local
384 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8188f_set_tx_power()
385 val32 &= 0xffff00ff; in rtl8188f_set_tx_power()
386 val32 |= (cck << 8); in rtl8188f_set_tx_power()
387 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8188f_set_tx_power()
389 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8188f_set_tx_power()
390 val32 &= 0xff; in rtl8188f_set_tx_power()
391 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8188f_set_tx_power()
392 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8188f_set_tx_power()
446 u32 val32, initial_gain, reg948; in rtl8188f_spur_calibration() local
448 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); in rtl8188f_spur_calibration()
449 val32 |= GENMASK(28, 24); in rtl8188f_spur_calibration()
450 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
453 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); in rtl8188f_spur_calibration()
454 val32 |= BIT(9); in rtl8188f_spur_calibration()
455 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
463 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8188f_spur_calibration()
464 val32 &= GENMASK(5, 3); in rtl8188f_spur_calibration()
465 hw_ctrl_s1 = val32 == BIT(3); in rtl8188f_spur_calibration()
474 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
475 val32 &= ~FPGA_RF_MODE_CCK; in rtl8188f_spur_calibration()
476 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
478 val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; in rtl8188f_spur_calibration()
479 val32 |= 0x30; in rtl8188f_spur_calibration()
480 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188f_spur_calibration()
502 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
503 val32 |= FPGA_RF_MODE_CCK; in rtl8188f_spur_calibration()
504 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
515 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); in rtl8188f_spur_calibration()
516 val32 |= BIT(28); in rtl8188f_spur_calibration()
517 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); in rtl8188f_spur_calibration()
525 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); in rtl8188f_spur_calibration()
526 val32 &= ~BIT(28); in rtl8188f_spur_calibration()
527 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); in rtl8188f_spur_calibration()
533 u32 val32; in rtl8188fu_config_channel() local
540 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8188fu_config_channel()
541 val32 &= ~MODE_AG_CHANNEL_MASK; in rtl8188fu_config_channel()
542 val32 |= channel; in rtl8188fu_config_channel()
543 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8188fu_config_channel()
549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
550 val32 &= ~FPGA_RF_MODE; in rtl8188fu_config_channel()
551 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; in rtl8188fu_config_channel()
552 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
554 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8188fu_config_channel()
555 val32 &= ~FPGA_RF_MODE; in rtl8188fu_config_channel()
556 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; in rtl8188fu_config_channel()
557 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188fu_config_channel()
560 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
561 val32 |= GENMASK(10, 8); in rtl8188fu_config_channel()
562 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
565 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
566 val32 |= BIT(14) | BIT(12); in rtl8188fu_config_channel()
567 val32 &= ~BIT(13); in rtl8188fu_config_channel()
568 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
571 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8188fu_config_channel()
572 val32 &= ~GENMASK(31, 30); in rtl8188fu_config_channel()
573 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8188fu_config_channel()
576 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8188fu_config_channel()
577 val32 &= ~BIT(29); in rtl8188fu_config_channel()
578 val32 |= BIT(28); in rtl8188fu_config_channel()
579 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8188fu_config_channel()
582 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); in rtl8188fu_config_channel()
583 val32 &= ~BIT(29); in rtl8188fu_config_channel()
584 val32 |= BIT(28); in rtl8188fu_config_channel()
585 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); in rtl8188fu_config_channel()
587 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); in rtl8188fu_config_channel()
588 val32 &= ~BIT(19); in rtl8188fu_config_channel()
589 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); in rtl8188fu_config_channel()
591 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); in rtl8188fu_config_channel()
592 val32 &= ~GENMASK(23, 20); in rtl8188fu_config_channel()
593 val32 |= BIT(21); in rtl8188fu_config_channel()
596 val32 |= BIT(20); in rtl8188fu_config_channel()
598 val32 |= BIT(22); in rtl8188fu_config_channel()
599 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); in rtl8188fu_config_channel()
612 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); in rtl8188fu_config_channel()
613 val32 &= ~CCK0_SIDEBAND; in rtl8188fu_config_channel()
615 val32 |= CCK0_SIDEBAND; in rtl8188fu_config_channel()
616 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); in rtl8188fu_config_channel()
618 val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); in rtl8188fu_config_channel()
619 val32 &= ~GENMASK(3, 0); in rtl8188fu_config_channel()
624 val32 |= subchannel; in rtl8188fu_config_channel()
625 rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); in rtl8188fu_config_channel()
627 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); in rtl8188fu_config_channel()
628 val32 &= ~RSR_RSC_BANDWIDTH_40M; in rtl8188fu_config_channel()
629 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8188fu_config_channel()
633 val32 = channel; in rtl8188fu_config_channel()
636 val32 |= MODE_AG_BW_20MHZ_8723B; in rtl8188fu_config_channel()
638 val32 |= MODE_AG_BW_40MHZ_8723B; in rtl8188fu_config_channel()
639 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8188fu_config_channel()
644 val32 = 0x00065; in rtl8188fu_config_channel()
646 val32 = 0x00025; in rtl8188fu_config_channel()
647 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); in rtl8188fu_config_channel()
651 val32 = 0x0; in rtl8188fu_config_channel()
653 val32 = 0x01000; in rtl8188fu_config_channel()
654 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); in rtl8188fu_config_channel()
664 u32 agg_rx, val32; in rtl8188fu_init_aggregation() local
667 val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); in rtl8188fu_init_aggregation()
668 val32 &= ~(0xf << 4); in rtl8188fu_init_aggregation()
669 val32 |= usb_tx_agg_desc_num << 4; in rtl8188fu_init_aggregation()
670 rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); in rtl8188fu_init_aggregation()
691 u32 val32; in rtl8188fu_init_statistics() local
700 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_init_statistics()
701 val32 |= 0xff; in rtl8188fu_init_statistics()
702 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_init_statistics()
705 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8188fu_init_statistics()
706 val32 &= ~(BIT(8) | BIT(9) | BIT(10)); in rtl8188fu_init_statistics()
707 val32 |= BIT(8); in rtl8188fu_init_statistics()
708 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8188fu_init_statistics()
711 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8188fu_init_statistics()
712 val32 |= BIT(7); in rtl8188fu_init_statistics()
713 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8188fu_init_statistics()
808 u32 val32; in rtl8188f_phy_lc_calibrate() local
817 val32 = lstf & ~OFDM_LSTF_MASK; in rtl8188f_phy_lc_calibrate()
818 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8188f_phy_lc_calibrate()
851 u32 reg_eac, reg_e94, reg_e9c, val32; in rtl8188fu_iqk_path_a() local
857 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
858 val32 &= 0x000000ff; in rtl8188fu_iqk_path_a()
859 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
864 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_iqk_path_a()
865 val32 |= 0x80000; in rtl8188fu_iqk_path_a()
866 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_iqk_path_a()
876 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
877 val32 &= 0x000000ff; in rtl8188fu_iqk_path_a()
878 val32 |= 0x80800000; in rtl8188fu_iqk_path_a()
879 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
900 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
901 val32 &= 0x000000ff; in rtl8188fu_iqk_path_a()
902 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
924 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; in rtl8188fu_rx_iqk_path_a() local
930 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
931 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
932 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
937 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_rx_iqk_path_a()
938 val32 |= 0x80000; in rtl8188fu_rx_iqk_path_a()
939 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_rx_iqk_path_a()
951 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
952 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
953 val32 |= 0x80800000; in rtl8188fu_rx_iqk_path_a()
954 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
981 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
982 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
983 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
999 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | in rtl8188fu_rx_iqk_path_a()
1001 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1006 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
1007 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
1008 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1010 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_rx_iqk_path_a()
1011 val32 |= 0x80000; in rtl8188fu_rx_iqk_path_a()
1012 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_rx_iqk_path_a()
1026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
1027 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
1028 val32 |= 0x80800000; in rtl8188fu_rx_iqk_path_a()
1029 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1055 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
1056 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
1057 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1081 u32 i, val32, rx_initial_gain, lok_result; in rtl8188fu_phy_iqcalibrate() local
1125 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); in rtl8188fu_phy_iqcalibrate()
1126 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); in rtl8188fu_phy_iqcalibrate()
1139 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); in rtl8188fu_phy_iqcalibrate()
1140 val32 |= 0x00ff0000; in rtl8188fu_phy_iqcalibrate()
1141 rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); in rtl8188fu_phy_iqcalibrate()
1144 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1145 val32 &= 0xff; in rtl8188fu_phy_iqcalibrate()
1146 val32 |= 0x80800000; in rtl8188fu_phy_iqcalibrate()
1147 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1154 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1155 val32 &= 0xff; in rtl8188fu_phy_iqcalibrate()
1156 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1158 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1160 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1162 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1164 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1172 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1174 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1176 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1178 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1187 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1188 val32 &= 0xff; in rtl8188fu_phy_iqcalibrate()
1189 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1199 val32 = 0x01000000; in rtl8188fu_phy_iqcalibrate()
1200 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); in rtl8188fu_phy_iqcalibrate()
1201 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); in rtl8188fu_phy_iqcalibrate()
1220 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1221 val32 &= 0xffffff00; in rtl8188fu_phy_iqcalibrate()
1222 val32 |= 0x50; in rtl8188fu_phy_iqcalibrate()
1223 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
1224 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1225 val32 &= 0xffffff00; in rtl8188fu_phy_iqcalibrate()
1226 val32 |= rx_initial_gain & 0xff; in rtl8188fu_phy_iqcalibrate()
1227 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
1352 u32 val32; in rtl8188f_emu_to_active() local
1362 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188f_emu_to_active()
1363 if (val32 & BIT(17)) in rtl8188f_emu_to_active()
1390 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188f_emu_to_active()
1391 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8188f_emu_to_active()
1412 u32 val32; in rtl8188fu_active_to_emu() local
1432 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188fu_active_to_emu()
1433 if ((val32 & APS_FSMCO_MAC_OFF) == 0) { in rtl8188fu_active_to_emu()
1472 u32 val32; in rtl8188fu_active_to_lps() local
1490 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8188fu_active_to_lps()
1491 if (!val32) { in rtl8188fu_active_to_lps()
1600 u32 val32; in rtl8188f_enable_rf() local
1621 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); in rtl8188f_enable_rf()
1622 val32 &= ~0xfc000; in rtl8188f_enable_rf()
1623 val32 |= val8 << 14; in rtl8188f_enable_rf()
1624 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); in rtl8188f_enable_rf()
1629 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_enable_rf()
1630 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); in rtl8188f_enable_rf()
1631 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; in rtl8188f_enable_rf()
1632 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_enable_rf()
1639 u32 val32; in rtl8188f_disable_rf() local
1641 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_disable_rf()
1642 val32 &= ~OFDM_RF_PATH_TX_MASK; in rtl8188f_disable_rf()
1643 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_disable_rf()
1652 u32 val32; in rtl8188f_usb_quirks() local
1658 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); in rtl8188f_usb_quirks()
1659 val32 |= TXDMA_OFFSET_DROP_DATA_EN; in rtl8188f_usb_quirks()
1660 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); in rtl8188f_usb_quirks()
1669 u32 val32; in rtl8188f_set_crystal_cap() local
1674 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); in rtl8188f_set_crystal_cap()
1680 FIELD_GET(XTAL1, val32), in rtl8188f_set_crystal_cap()
1681 FIELD_GET(XTAL0, val32), in rtl8188f_set_crystal_cap()
1684 val32 &= ~(XTAL1 | XTAL0); in rtl8188f_set_crystal_cap()
1685 val32 |= FIELD_PREP(XTAL1, crystal_cap) | in rtl8188f_set_crystal_cap()
1687 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); in rtl8188f_set_crystal_cap()