Lines Matching refs:val32
442 u32 val32, rsr; in rtl8188eu_config_channel() local
457 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188eu_config_channel()
458 val32 &= ~FPGA_RF_MODE; in rtl8188eu_config_channel()
459 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
461 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8188eu_config_channel()
462 val32 &= ~FPGA_RF_MODE; in rtl8188eu_config_channel()
463 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188eu_config_channel()
484 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188eu_config_channel()
485 val32 |= FPGA_RF_MODE; in rtl8188eu_config_channel()
486 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
488 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8188eu_config_channel()
489 val32 |= FPGA_RF_MODE; in rtl8188eu_config_channel()
490 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188eu_config_channel()
496 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); in rtl8188eu_config_channel()
497 val32 &= ~CCK0_SIDEBAND; in rtl8188eu_config_channel()
499 val32 |= CCK0_SIDEBAND; in rtl8188eu_config_channel()
500 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); in rtl8188eu_config_channel()
502 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); in rtl8188eu_config_channel()
503 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ in rtl8188eu_config_channel()
505 val32 |= OFDM_LSTF_PRIME_CH_LOW; in rtl8188eu_config_channel()
507 val32 |= OFDM_LSTF_PRIME_CH_HIGH; in rtl8188eu_config_channel()
508 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8188eu_config_channel()
510 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); in rtl8188eu_config_channel()
511 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); in rtl8188eu_config_channel()
513 val32 |= FPGA0_PS_UPPER_CHANNEL; in rtl8188eu_config_channel()
515 val32 |= FPGA0_PS_LOWER_CHANNEL; in rtl8188eu_config_channel()
516 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); in rtl8188eu_config_channel()
524 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); in rtl8188eu_config_channel()
525 u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK); in rtl8188eu_config_channel()
526 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); in rtl8188eu_config_channel()
530 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); in rtl8188eu_config_channel()
531 val32 &= ~MODE_AG_BW_MASK; in rtl8188eu_config_channel()
533 val32 |= MODE_AG_BW_40MHZ_8723B; in rtl8188eu_config_channel()
535 val32 |= MODE_AG_BW_20MHZ_8723B; in rtl8188eu_config_channel()
536 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); in rtl8188eu_config_channel()
662 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; in rtl8188eu_rx_iqk_path_a() local
666 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
667 u32p_replace_bits(&val32, 0, 0xffffff00); in rtl8188eu_rx_iqk_path_a()
668 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
677 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
678 u32p_replace_bits(&val32, 0x808000, 0xffffff00); in rtl8188eu_rx_iqk_path_a()
679 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
713 val32 = 0x80007c00 | in rtl8188eu_rx_iqk_path_a()
715 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8188eu_rx_iqk_path_a()
718 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
719 u32p_replace_bits(&val32, 0, 0xffffff00); in rtl8188eu_rx_iqk_path_a()
720 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
728 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
729 u32p_replace_bits(&val32, 0x808000, 0xffffff00); in rtl8188eu_rx_iqk_path_a()
730 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
770 u32 i, val32; in rtl8188eu_phy_iqcalibrate() local
811 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); in rtl8188eu_phy_iqcalibrate()
812 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); in rtl8188eu_phy_iqcalibrate()
824 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8188eu_phy_iqcalibrate()
825 u32p_replace_bits(&val32, 0xf, 0x0f000000); in rtl8188eu_phy_iqcalibrate()
826 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8188eu_phy_iqcalibrate()
833 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8188eu_phy_iqcalibrate()
834 val32 |= (FPGA0_RF_PAPE | in rtl8188eu_phy_iqcalibrate()
836 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8188eu_phy_iqcalibrate()
839 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8188eu_phy_iqcalibrate()
840 val32 &= ~BIT(10); in rtl8188eu_phy_iqcalibrate()
841 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8188eu_phy_iqcalibrate()
842 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8188eu_phy_iqcalibrate()
843 val32 &= ~BIT(10); in rtl8188eu_phy_iqcalibrate()
844 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8188eu_phy_iqcalibrate()
850 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_phy_iqcalibrate()
851 u32p_replace_bits(&val32, 0x808000, 0xffffff00); in rtl8188eu_phy_iqcalibrate()
852 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_phy_iqcalibrate()
859 val32 = rtl8xxxu_read32(priv, in rtl8188eu_phy_iqcalibrate()
861 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8188eu_phy_iqcalibrate()
862 val32 = rtl8xxxu_read32(priv, in rtl8188eu_phy_iqcalibrate()
864 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8188eu_phy_iqcalibrate()
875 val32 = rtl8xxxu_read32(priv, in rtl8188eu_phy_iqcalibrate()
877 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8188eu_phy_iqcalibrate()
878 val32 = rtl8xxxu_read32(priv, in rtl8188eu_phy_iqcalibrate()
880 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8188eu_phy_iqcalibrate()
890 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_phy_iqcalibrate()
891 u32p_replace_bits(&val32, 0, 0xffffff00); in rtl8188eu_phy_iqcalibrate()
892 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_phy_iqcalibrate()
1021 u32 val32; in rtl8188e_emu_to_active() local
1027 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188e_emu_to_active()
1028 if (val32 & BIT(17)) in rtl8188e_emu_to_active()
1045 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); in rtl8188e_emu_to_active()
1046 val32 |= BIT(23); in rtl8188e_emu_to_active()
1047 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); in rtl8188e_emu_to_active()
1060 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188e_emu_to_active()
1061 val32 |= APS_FSMCO_MAC_ENABLE; in rtl8188e_emu_to_active()
1062 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8188e_emu_to_active()
1065 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188e_emu_to_active()
1066 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8188e_emu_to_active()
1106 u32 val32; in rtl8188eu_emu_to_disabled() local
1110 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); in rtl8188eu_emu_to_disabled()
1111 val32 |= BIT(23); in rtl8188eu_emu_to_disabled()
1112 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); in rtl8188eu_emu_to_disabled()
1138 u32 val32; in rtl8188eu_active_to_lps() local
1147 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8188eu_active_to_lps()
1148 if (!val32) { in rtl8188eu_active_to_lps()
1280 u32 val32; in rtl8188e_enable_rf() local
1284 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188e_enable_rf()
1285 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); in rtl8188e_enable_rf()
1286 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; in rtl8188e_enable_rf()
1287 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188e_enable_rf()
1294 u32 val32; in rtl8188e_disable_rf() local
1296 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188e_disable_rf()
1297 val32 &= ~OFDM_RF_PATH_TX_MASK; in rtl8188e_disable_rf()
1298 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188e_disable_rf()