Lines Matching refs:rt2x00mmio_register_write
72 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
100 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_read()
130 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); in rt61pci_rf_write()
154 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt61pci_mcu_request()
159 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); in rt61pci_mcu_request()
193 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); in rt61pci_eepromregister_write()
201 .write = rt2x00mmio_register_write,
289 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
379 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); in rt61pci_config_pairwise_key()
407 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); in rt61pci_config_pairwise_key()
416 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); in rt61pci_config_pairwise_key()
451 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_filter()
467 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_intf()
499 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_erp()
506 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_erp()
510 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5, in rt61pci_config_erp()
517 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_erp()
523 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_config_erp()
529 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); in rt61pci_config_erp()
630 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_config_antenna_2529_rx()
736 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); in rt61pci_config_ant()
844 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_retry_limit()
865 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
868 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
870 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
872 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); in rt61pci_config_ps()
873 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); in rt61pci_config_ps()
882 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
884 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
886 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); in rt61pci_config_ps()
887 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); in rt61pci_config_ps()
1050 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_start_queue()
1057 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_start_queue()
1073 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1078 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1083 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1088 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1104 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1109 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1114 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1119 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1124 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_stop_queue()
1131 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_stop_queue()
1225 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1226 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_load_firmware()
1227 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); in rt61pci_load_firmware()
1228 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0); in rt61pci_load_firmware()
1236 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1242 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1245 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1270 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1275 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1279 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1344 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); in rt61pci_init_queues()
1349 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); in rt61pci_init_queues()
1355 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); in rt61pci_init_queues()
1361 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); in rt61pci_init_queues()
1367 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); in rt61pci_init_queues()
1373 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); in rt61pci_init_queues()
1380 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); in rt61pci_init_queues()
1386 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); in rt61pci_init_queues()
1393 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); in rt61pci_init_queues()
1400 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); in rt61pci_init_queues()
1404 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_init_queues()
1417 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_init_registers()
1428 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); in rt61pci_init_registers()
1442 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); in rt61pci_init_registers()
1454 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); in rt61pci_init_registers()
1461 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); in rt61pci_init_registers()
1468 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); in rt61pci_init_registers()
1477 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_init_registers()
1479 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); in rt61pci_init_registers()
1481 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); in rt61pci_init_registers()
1485 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_init_registers()
1487 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); in rt61pci_init_registers()
1492 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); in rt61pci_init_registers()
1498 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000); in rt61pci_init_registers()
1499 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000); in rt61pci_init_registers()
1500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000); in rt61pci_init_registers()
1502 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); in rt61pci_init_registers()
1503 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); in rt61pci_init_registers()
1504 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606); in rt61pci_init_registers()
1505 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); in rt61pci_init_registers()
1507 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); in rt61pci_init_registers()
1509 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); in rt61pci_init_registers()
1511 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_init_registers()
1519 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0); in rt61pci_init_registers()
1520 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0); in rt61pci_init_registers()
1521 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0); in rt61pci_init_registers()
1522 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0); in rt61pci_init_registers()
1539 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1544 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1548 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1633 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1636 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1651 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1663 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1695 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_enable_radio()
1705 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818); in rt61pci_disable_radio()
1719 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1731 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1888 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1908 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_write_beacon()
1925 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); in rt61pci_write_beacon()
1928 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1949 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_clear_beacon()
1954 rt2x00mmio_register_write(rt2x00dev, in rt61pci_clear_beacon()
1960 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_clear_beacon()
2170 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2188 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_enable_mcu_interrupt()
2226 rt2x00mmio_register_write(rt2x00dev, in rt61pci_autowake_tasklet()
2243 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); in rt61pci_interrupt()
2246 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_interrupt()
2285 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
2289 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_interrupt()
2747 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); in rt61pci_probe_hw()
2766 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_probe_hw()
2839 rt2x00mmio_register_write(rt2x00dev, offset, reg); in rt61pci_conf_tx()
2847 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); in rt61pci_conf_tx()
2851 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); in rt61pci_conf_tx()
2855 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); in rt61pci_conf_tx()