Lines Matching refs:rt2x00dev
54 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, in rt61pci_bbp_write() argument
59 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
65 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_write()
72 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
75 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
78 static u8 rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, in rt61pci_bbp_read() argument
84 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
94 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_read()
100 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_read()
102 WAIT_FOR_BBP(rt2x00dev, ®); in rt61pci_bbp_read()
107 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
112 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, in rt61pci_rf_write() argument
117 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
123 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt61pci_rf_write()
130 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); in rt61pci_rf_write()
131 rt2x00_rf_write(rt2x00dev, word, value); in rt61pci_rf_write()
134 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
137 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, in rt61pci_mcu_request() argument
143 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
149 if (WAIT_FOR_MCU(rt2x00dev, ®)) { in rt61pci_mcu_request()
154 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt61pci_mcu_request()
156 reg = rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR); in rt61pci_mcu_request()
159 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); in rt61pci_mcu_request()
162 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
168 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_read() local
171 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); in rt61pci_eepromregister_read()
183 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_write() local
193 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); in rt61pci_eepromregister_write()
231 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) in rt61pci_rfkill_poll() argument
235 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_rfkill_poll()
247 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ); in rt61pci_brightness_set()
249 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); in rt61pci_brightness_set()
252 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
255 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
256 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
257 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
259 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
261 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
264 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
265 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
266 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
273 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, in rt61pci_brightness_set()
286 reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14); in rt61pci_blink_set()
289 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
294 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, in rt61pci_init_led() argument
298 led->rt2x00dev = rt2x00dev; in rt61pci_init_led()
309 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, in rt61pci_config_shared_key() argument
321 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, in rt61pci_config_pairwise_key() argument
340 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); in rt61pci_config_pairwise_key()
343 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); in rt61pci_config_pairwise_key()
365 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
369 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
377 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR4); in rt61pci_config_pairwise_key()
379 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); in rt61pci_config_pairwise_key()
402 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); in rt61pci_config_pairwise_key()
407 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); in rt61pci_config_pairwise_key()
411 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); in rt61pci_config_pairwise_key()
416 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); in rt61pci_config_pairwise_key()
422 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, in rt61pci_config_filter() argument
433 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_config_filter()
441 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); in rt61pci_config_filter()
443 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && in rt61pci_config_filter()
444 !rt2x00dev->intf_ap_count); in rt61pci_config_filter()
451 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_filter()
454 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, in rt61pci_config_intf() argument
465 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_config_intf()
467 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_intf()
475 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2, in rt61pci_config_intf()
484 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4, in rt61pci_config_intf()
490 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, in rt61pci_config_erp() argument
496 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_config_erp()
499 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_erp()
502 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); in rt61pci_config_erp()
506 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_erp()
510 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5, in rt61pci_config_erp()
514 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_config_erp()
517 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_erp()
521 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); in rt61pci_config_erp()
523 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_config_erp()
525 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR8); in rt61pci_config_erp()
529 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); in rt61pci_config_erp()
533 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_5x() argument
540 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_antenna_5x()
541 r4 = rt61pci_bbp_read(rt2x00dev, 4); in rt61pci_config_antenna_5x()
542 r77 = rt61pci_bbp_read(rt2x00dev, 77); in rt61pci_config_antenna_5x()
544 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); in rt61pci_config_antenna_5x()
553 (rt2x00dev->curr_band != NL80211_BAND_5GHZ)); in rt61pci_config_antenna_5x()
558 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
567 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
574 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_5x()
575 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_5x()
576 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_5x()
579 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2x() argument
586 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_antenna_2x()
587 r4 = rt61pci_bbp_read(rt2x00dev, 4); in rt61pci_config_antenna_2x()
588 r77 = rt61pci_bbp_read(rt2x00dev, 77); in rt61pci_config_antenna_2x()
590 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); in rt61pci_config_antenna_2x()
592 !rt2x00_has_cap_frame_type(rt2x00dev)); in rt61pci_config_antenna_2x()
612 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_2x()
613 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_2x()
614 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_2x()
617 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2529_rx() argument
622 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_config_antenna_2529_rx()
630 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_config_antenna_2529_rx()
633 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2529() argument
640 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_antenna_2529()
641 r4 = rt61pci_bbp_read(rt2x00dev, 4); in rt61pci_config_antenna_2529()
642 r77 = rt61pci_bbp_read(rt2x00dev, 77); in rt61pci_config_antenna_2529()
651 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); in rt61pci_config_antenna_2529()
663 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); in rt61pci_config_antenna_2529()
667 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_2529()
668 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_2529()
669 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_2529()
703 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, in rt61pci_config_ant() argument
718 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_config_ant()
720 lna = rt2x00_has_cap_external_lna_a(rt2x00dev); in rt61pci_config_ant()
723 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev); in rt61pci_config_ant()
727 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); in rt61pci_config_ant()
729 reg = rt2x00mmio_register_read(rt2x00dev, PHY_CSR0); in rt61pci_config_ant()
732 rt2x00dev->curr_band == NL80211_BAND_2GHZ); in rt61pci_config_ant()
734 rt2x00dev->curr_band == NL80211_BAND_5GHZ); in rt61pci_config_ant()
736 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); in rt61pci_config_ant()
738 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) in rt61pci_config_ant()
739 rt61pci_config_antenna_5x(rt2x00dev, ant); in rt61pci_config_ant()
740 else if (rt2x00_rf(rt2x00dev, RF2527)) in rt61pci_config_ant()
741 rt61pci_config_antenna_2x(rt2x00dev, ant); in rt61pci_config_ant()
742 else if (rt2x00_rf(rt2x00dev, RF2529)) { in rt61pci_config_ant()
743 if (rt2x00_has_cap_double_antenna(rt2x00dev)) in rt61pci_config_ant()
744 rt61pci_config_antenna_2x(rt2x00dev, ant); in rt61pci_config_ant()
746 rt61pci_config_antenna_2529(rt2x00dev, ant); in rt61pci_config_ant()
750 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, in rt61pci_config_lna_gain() argument
757 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) in rt61pci_config_lna_gain()
760 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); in rt61pci_config_lna_gain()
763 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) in rt61pci_config_lna_gain()
766 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); in rt61pci_config_lna_gain()
770 rt2x00dev->lna_gain = lna_gain; in rt61pci_config_lna_gain()
773 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, in rt61pci_config_channel() argument
781 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt61pci_config_channel()
783 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); in rt61pci_config_channel()
785 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_channel()
787 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_channel()
794 rt61pci_bbp_write(rt2x00dev, 94, r94); in rt61pci_config_channel()
796 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
797 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
798 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
799 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
803 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
804 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
805 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); in rt61pci_config_channel()
806 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
810 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
811 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
812 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
813 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
818 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, in rt61pci_config_txpower() argument
823 rf.rf1 = rt2x00_rf_read(rt2x00dev, 1); in rt61pci_config_txpower()
824 rf.rf2 = rt2x00_rf_read(rt2x00dev, 2); in rt61pci_config_txpower()
825 rf.rf3 = rt2x00_rf_read(rt2x00dev, 3); in rt61pci_config_txpower()
826 rf.rf4 = rt2x00_rf_read(rt2x00dev, 4); in rt61pci_config_txpower()
828 rt61pci_config_channel(rt2x00dev, &rf, txpower); in rt61pci_config_txpower()
831 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, in rt61pci_config_retry_limit() argument
836 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); in rt61pci_config_retry_limit()
844 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_retry_limit()
847 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, in rt61pci_config_ps() argument
856 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); in rt61pci_config_ps()
858 rt2x00dev->beacon_int - 10); in rt61pci_config_ps()
865 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
868 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
870 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
872 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); in rt61pci_config_ps()
873 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); in rt61pci_config_ps()
875 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); in rt61pci_config_ps()
877 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); in rt61pci_config_ps()
882 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
884 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
886 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); in rt61pci_config_ps()
887 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); in rt61pci_config_ps()
889 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); in rt61pci_config_ps()
893 static void rt61pci_config(struct rt2x00_dev *rt2x00dev, in rt61pci_config() argument
898 rt61pci_config_lna_gain(rt2x00dev, libconf); in rt61pci_config()
901 rt61pci_config_channel(rt2x00dev, &libconf->rf, in rt61pci_config()
905 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); in rt61pci_config()
907 rt61pci_config_retry_limit(rt2x00dev, libconf); in rt61pci_config()
909 rt61pci_config_ps(rt2x00dev, libconf); in rt61pci_config()
915 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, in rt61pci_link_stats() argument
923 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); in rt61pci_link_stats()
929 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); in rt61pci_link_stats()
933 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, in rt61pci_set_vgc() argument
937 rt61pci_bbp_write(rt2x00dev, 17, vgc_level); in rt61pci_set_vgc()
943 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev, in rt61pci_reset_tuner() argument
946 rt61pci_set_vgc(rt2x00dev, qual, 0x20); in rt61pci_reset_tuner()
949 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, in rt61pci_link_tuner() argument
958 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_link_tuner()
961 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { in rt61pci_link_tuner()
968 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { in rt61pci_link_tuner()
978 if (!rt2x00dev->intf_associated) in rt61pci_link_tuner()
985 rt61pci_set_vgc(rt2x00dev, qual, 0x60); in rt61pci_link_tuner()
993 rt61pci_set_vgc(rt2x00dev, qual, up_bound); in rt61pci_link_tuner()
1001 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10); in rt61pci_link_tuner()
1009 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08); in rt61pci_link_tuner()
1022 rt61pci_set_vgc(rt2x00dev, qual, up_bound); in rt61pci_link_tuner()
1033 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); in rt61pci_link_tuner()
1035 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); in rt61pci_link_tuner()
1043 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_start_queue() local
1048 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_start_queue()
1050 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_start_queue()
1053 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_start_queue()
1057 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_start_queue()
1066 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_kick_queue() local
1071 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1073 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1076 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1078 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1081 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1083 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1086 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1088 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1097 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_stop_queue() local
1102 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1104 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1107 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1109 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1112 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1114 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1117 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1119 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1122 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_stop_queue()
1124 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_stop_queue()
1127 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_stop_queue()
1131 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_stop_queue()
1136 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_stop_queue()
1146 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) in rt61pci_get_firmware_name() argument
1151 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); in rt61pci_get_firmware_name()
1170 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev, in rt61pci_check_firmware() argument
1199 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, in rt61pci_load_firmware() argument
1209 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); in rt61pci_load_firmware()
1216 rt2x00_err(rt2x00dev, "Unstable hardware\n"); in rt61pci_load_firmware()
1225 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1226 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_load_firmware()
1227 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); in rt61pci_load_firmware()
1228 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0); in rt61pci_load_firmware()
1236 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1238 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, in rt61pci_load_firmware()
1242 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1245 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1248 reg = rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR); in rt61pci_load_firmware()
1255 rt2x00_err(rt2x00dev, "MCU Control register not ready\n"); in rt61pci_load_firmware()
1270 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1272 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_load_firmware()
1275 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1277 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_load_firmware()
1279 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1327 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) in rt61pci_init_queues() argument
1335 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0); in rt61pci_init_queues()
1337 rt2x00dev->tx[0].limit); in rt61pci_init_queues()
1339 rt2x00dev->tx[1].limit); in rt61pci_init_queues()
1341 rt2x00dev->tx[2].limit); in rt61pci_init_queues()
1343 rt2x00dev->tx[3].limit); in rt61pci_init_queues()
1344 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); in rt61pci_init_queues()
1346 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1); in rt61pci_init_queues()
1348 rt2x00dev->tx[0].desc_size / 4); in rt61pci_init_queues()
1349 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); in rt61pci_init_queues()
1351 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt61pci_init_queues()
1352 reg = rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR); in rt61pci_init_queues()
1355 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); in rt61pci_init_queues()
1357 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt61pci_init_queues()
1358 reg = rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR); in rt61pci_init_queues()
1361 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); in rt61pci_init_queues()
1363 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; in rt61pci_init_queues()
1364 reg = rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR); in rt61pci_init_queues()
1367 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); in rt61pci_init_queues()
1369 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; in rt61pci_init_queues()
1370 reg = rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR); in rt61pci_init_queues()
1373 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); in rt61pci_init_queues()
1375 reg = rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR); in rt61pci_init_queues()
1376 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1378 rt2x00dev->rx->desc_size / 4); in rt61pci_init_queues()
1380 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); in rt61pci_init_queues()
1382 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt61pci_init_queues()
1383 reg = rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR); in rt61pci_init_queues()
1386 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); in rt61pci_init_queues()
1388 reg = rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR); in rt61pci_init_queues()
1393 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); in rt61pci_init_queues()
1395 reg = rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR); in rt61pci_init_queues()
1400 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); in rt61pci_init_queues()
1402 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); in rt61pci_init_queues()
1404 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_init_queues()
1409 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) in rt61pci_init_registers() argument
1413 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_init_registers()
1417 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_init_registers()
1419 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1); in rt61pci_init_registers()
1428 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); in rt61pci_init_registers()
1433 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2); in rt61pci_init_registers()
1442 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); in rt61pci_init_registers()
1447 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3); in rt61pci_init_registers()
1454 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); in rt61pci_init_registers()
1456 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7); in rt61pci_init_registers()
1461 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); in rt61pci_init_registers()
1463 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8); in rt61pci_init_registers()
1468 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); in rt61pci_init_registers()
1470 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_init_registers()
1477 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_init_registers()
1479 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); in rt61pci_init_registers()
1481 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); in rt61pci_init_registers()
1483 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); in rt61pci_init_registers()
1485 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_init_registers()
1487 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); in rt61pci_init_registers()
1489 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt61pci_init_registers()
1492 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); in rt61pci_init_registers()
1498 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000); in rt61pci_init_registers()
1499 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000); in rt61pci_init_registers()
1500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000); in rt61pci_init_registers()
1502 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); in rt61pci_init_registers()
1503 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); in rt61pci_init_registers()
1504 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606); in rt61pci_init_registers()
1505 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); in rt61pci_init_registers()
1507 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); in rt61pci_init_registers()
1509 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); in rt61pci_init_registers()
1511 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_init_registers()
1519 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0); in rt61pci_init_registers()
1520 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0); in rt61pci_init_registers()
1521 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0); in rt61pci_init_registers()
1522 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0); in rt61pci_init_registers()
1529 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); in rt61pci_init_registers()
1530 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); in rt61pci_init_registers()
1531 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR2); in rt61pci_init_registers()
1536 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1539 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1541 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1544 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1546 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1548 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1553 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) in rt61pci_wait_bbp_ready() argument
1559 value = rt61pci_bbp_read(rt2x00dev, 0); in rt61pci_wait_bbp_ready()
1565 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); in rt61pci_wait_bbp_ready()
1569 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) in rt61pci_init_bbp() argument
1576 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) in rt61pci_init_bbp()
1579 rt61pci_bbp_write(rt2x00dev, 3, 0x00); in rt61pci_init_bbp()
1580 rt61pci_bbp_write(rt2x00dev, 15, 0x30); in rt61pci_init_bbp()
1581 rt61pci_bbp_write(rt2x00dev, 21, 0xc8); in rt61pci_init_bbp()
1582 rt61pci_bbp_write(rt2x00dev, 22, 0x38); in rt61pci_init_bbp()
1583 rt61pci_bbp_write(rt2x00dev, 23, 0x06); in rt61pci_init_bbp()
1584 rt61pci_bbp_write(rt2x00dev, 24, 0xfe); in rt61pci_init_bbp()
1585 rt61pci_bbp_write(rt2x00dev, 25, 0x0a); in rt61pci_init_bbp()
1586 rt61pci_bbp_write(rt2x00dev, 26, 0x0d); in rt61pci_init_bbp()
1587 rt61pci_bbp_write(rt2x00dev, 34, 0x12); in rt61pci_init_bbp()
1588 rt61pci_bbp_write(rt2x00dev, 37, 0x07); in rt61pci_init_bbp()
1589 rt61pci_bbp_write(rt2x00dev, 39, 0xf8); in rt61pci_init_bbp()
1590 rt61pci_bbp_write(rt2x00dev, 41, 0x60); in rt61pci_init_bbp()
1591 rt61pci_bbp_write(rt2x00dev, 53, 0x10); in rt61pci_init_bbp()
1592 rt61pci_bbp_write(rt2x00dev, 54, 0x18); in rt61pci_init_bbp()
1593 rt61pci_bbp_write(rt2x00dev, 60, 0x10); in rt61pci_init_bbp()
1594 rt61pci_bbp_write(rt2x00dev, 61, 0x04); in rt61pci_init_bbp()
1595 rt61pci_bbp_write(rt2x00dev, 62, 0x04); in rt61pci_init_bbp()
1596 rt61pci_bbp_write(rt2x00dev, 75, 0xfe); in rt61pci_init_bbp()
1597 rt61pci_bbp_write(rt2x00dev, 86, 0xfe); in rt61pci_init_bbp()
1598 rt61pci_bbp_write(rt2x00dev, 88, 0xfe); in rt61pci_init_bbp()
1599 rt61pci_bbp_write(rt2x00dev, 90, 0x0f); in rt61pci_init_bbp()
1600 rt61pci_bbp_write(rt2x00dev, 99, 0x00); in rt61pci_init_bbp()
1601 rt61pci_bbp_write(rt2x00dev, 102, 0x16); in rt61pci_init_bbp()
1602 rt61pci_bbp_write(rt2x00dev, 107, 0x04); in rt61pci_init_bbp()
1605 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i); in rt61pci_init_bbp()
1610 rt61pci_bbp_write(rt2x00dev, reg_id, value); in rt61pci_init_bbp()
1620 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, in rt61pci_toggle_irq() argument
1632 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); in rt61pci_toggle_irq()
1633 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1635 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); in rt61pci_toggle_irq()
1636 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1643 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1645 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_toggle_irq()
1651 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1653 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_toggle_irq()
1663 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1665 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1671 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt61pci_toggle_irq()
1672 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt61pci_toggle_irq()
1673 tasklet_kill(&rt2x00dev->autowake_tasklet); in rt61pci_toggle_irq()
1674 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_toggle_irq()
1678 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) in rt61pci_enable_radio() argument
1685 if (unlikely(rt61pci_init_queues(rt2x00dev) || in rt61pci_enable_radio()
1686 rt61pci_init_registers(rt2x00dev) || in rt61pci_enable_radio()
1687 rt61pci_init_bbp(rt2x00dev))) in rt61pci_enable_radio()
1693 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); in rt61pci_enable_radio()
1695 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_enable_radio()
1700 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) in rt61pci_disable_radio() argument
1705 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818); in rt61pci_disable_radio()
1708 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) in rt61pci_set_state() argument
1716 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); in rt61pci_set_state()
1719 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1727 reg2 = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); in rt61pci_set_state()
1731 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1738 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, in rt61pci_set_device_state() argument
1745 retval = rt61pci_enable_radio(rt2x00dev); in rt61pci_set_device_state()
1748 rt61pci_disable_radio(rt2x00dev); in rt61pci_set_device_state()
1752 rt61pci_toggle_irq(rt2x00dev, state); in rt61pci_set_device_state()
1758 retval = rt61pci_set_state(rt2x00dev, state); in rt61pci_set_device_state()
1766 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", in rt61pci_set_device_state()
1815 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); in rt61pci_write_tx_desc()
1875 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_write_beacon() local
1885 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_write_beacon()
1888 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1898 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); in rt61pci_write_beacon()
1905 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); in rt61pci_write_beacon()
1908 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_write_beacon()
1913 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base, in rt61pci_write_beacon()
1915 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, in rt61pci_write_beacon()
1925 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); in rt61pci_write_beacon()
1928 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1939 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_clear_beacon() local
1946 orig_reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_clear_beacon()
1949 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_clear_beacon()
1954 rt2x00mmio_register_write(rt2x00dev, in rt61pci_clear_beacon()
1960 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_clear_beacon()
1966 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) in rt61pci_agc_to_rssi() argument
1968 u8 offset = rt2x00dev->lna_gain; in rt61pci_agc_to_rssi()
1986 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_agc_to_rssi()
1997 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_fill_rxdone() local
2045 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); in rt61pci_fill_rxdone()
2059 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) in rt61pci_txdone() argument
2081 for (i = 0; i < rt2x00dev->tx->limit; i++) { in rt61pci_txdone()
2082 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR4); in rt61pci_txdone()
2091 queue = rt2x00queue_get_tx_queue(rt2x00dev, type); in rt61pci_txdone()
2116 rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n", in rt61pci_txdone()
2150 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev) in rt61pci_wakeup() argument
2152 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf }; in rt61pci_wakeup()
2154 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); in rt61pci_wakeup()
2157 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, in rt61pci_enable_interrupt() argument
2166 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2168 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_enable_interrupt()
2170 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2172 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2175 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev, in rt61pci_enable_mcu_interrupt() argument
2184 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2186 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_enable_mcu_interrupt()
2188 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_enable_mcu_interrupt()
2190 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2195 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, in rt61pci_txstatus_tasklet() local
2198 rt61pci_txdone(rt2x00dev); in rt61pci_txstatus_tasklet()
2199 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_txstatus_tasklet()
2200 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE); in rt61pci_txstatus_tasklet()
2205 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet); in rt61pci_tbtt_tasklet() local
2206 rt2x00lib_beacondone(rt2x00dev); in rt61pci_tbtt_tasklet()
2207 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_tbtt_tasklet()
2208 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE); in rt61pci_tbtt_tasklet()
2213 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, in rt61pci_rxdone_tasklet() local
2215 if (rt2x00mmio_rxdone(rt2x00dev)) in rt61pci_rxdone_tasklet()
2216 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_rxdone_tasklet()
2217 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_rxdone_tasklet()
2218 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE); in rt61pci_rxdone_tasklet()
2223 struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, in rt61pci_autowake_tasklet() local
2225 rt61pci_wakeup(rt2x00dev); in rt61pci_autowake_tasklet()
2226 rt2x00mmio_register_write(rt2x00dev, in rt61pci_autowake_tasklet()
2228 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_autowake_tasklet()
2229 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP); in rt61pci_autowake_tasklet()
2234 struct rt2x00_dev *rt2x00dev = dev_instance; in rt61pci_interrupt() local
2242 reg_mcu = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); in rt61pci_interrupt()
2243 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); in rt61pci_interrupt()
2245 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); in rt61pci_interrupt()
2246 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_interrupt()
2251 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_interrupt()
2258 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_interrupt()
2261 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt61pci_interrupt()
2264 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt61pci_interrupt()
2267 tasklet_schedule(&rt2x00dev->autowake_tasklet); in rt61pci_interrupt()
2281 spin_lock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2283 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_interrupt()
2285 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
2287 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_interrupt()
2289 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_interrupt()
2291 spin_unlock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2299 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) in rt61pci_validate_eeprom() argument
2307 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); in rt61pci_validate_eeprom()
2309 eeprom.data = rt2x00dev; in rt61pci_validate_eeprom()
2319 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt61pci_validate_eeprom()
2325 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); in rt61pci_validate_eeprom()
2326 rt2x00lib_set_mac_address(rt2x00dev, mac); in rt61pci_validate_eeprom()
2328 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt61pci_validate_eeprom()
2339 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); in rt61pci_validate_eeprom()
2340 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); in rt61pci_validate_eeprom()
2343 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); in rt61pci_validate_eeprom()
2352 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); in rt61pci_validate_eeprom()
2353 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); in rt61pci_validate_eeprom()
2356 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); in rt61pci_validate_eeprom()
2360 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); in rt61pci_validate_eeprom()
2361 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); in rt61pci_validate_eeprom()
2364 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); in rt61pci_validate_eeprom()
2368 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); in rt61pci_validate_eeprom()
2369 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); in rt61pci_validate_eeprom()
2372 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); in rt61pci_validate_eeprom()
2376 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); in rt61pci_validate_eeprom()
2377 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); in rt61pci_validate_eeprom()
2385 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); in rt61pci_validate_eeprom()
2388 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); in rt61pci_validate_eeprom()
2392 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); in rt61pci_validate_eeprom()
2393 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); in rt61pci_validate_eeprom()
2401 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); in rt61pci_validate_eeprom()
2407 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) in rt61pci_init_eeprom() argument
2416 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt61pci_init_eeprom()
2422 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); in rt61pci_init_eeprom()
2423 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), in rt61pci_init_eeprom()
2426 if (!rt2x00_rf(rt2x00dev, RF5225) && in rt61pci_init_eeprom()
2427 !rt2x00_rf(rt2x00dev, RF5325) && in rt61pci_init_eeprom()
2428 !rt2x00_rf(rt2x00dev, RF2527) && in rt61pci_init_eeprom()
2429 !rt2x00_rf(rt2x00dev, RF2529)) { in rt61pci_init_eeprom()
2430 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); in rt61pci_init_eeprom()
2438 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2443 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2445 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2452 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2458 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2463 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); in rt61pci_init_eeprom()
2465 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2467 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); in rt61pci_init_eeprom()
2472 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); in rt61pci_init_eeprom()
2475 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2477 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2484 if (rt2x00_rf(rt2x00dev, RF2529) && in rt61pci_init_eeprom()
2485 !rt2x00_has_cap_double_antenna(rt2x00dev)) { in rt61pci_init_eeprom()
2486 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2488 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2492 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2494 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2503 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); in rt61pci_init_eeprom()
2506 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt61pci_init_eeprom()
2507 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); in rt61pci_init_eeprom()
2509 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt61pci_init_eeprom()
2512 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); in rt61pci_init_eeprom()
2513 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, in rt61pci_init_eeprom()
2516 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, in rt61pci_init_eeprom()
2519 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, in rt61pci_init_eeprom()
2522 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, in rt61pci_init_eeprom()
2525 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, in rt61pci_init_eeprom()
2528 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, in rt61pci_init_eeprom()
2530 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, in rt61pci_init_eeprom()
2533 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, in rt61pci_init_eeprom()
2655 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) in rt61pci_probe_hw_mode() argument
2657 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt61pci_probe_hw_mode()
2665 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; in rt61pci_probe_hw_mode()
2670 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); in rt61pci_probe_hw_mode()
2671 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); in rt61pci_probe_hw_mode()
2672 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); in rt61pci_probe_hw_mode()
2673 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); in rt61pci_probe_hw_mode()
2675 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt61pci_probe_hw_mode()
2676 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt61pci_probe_hw_mode()
2677 rt2x00_eeprom_addr(rt2x00dev, in rt61pci_probe_hw_mode()
2689 rt2x00dev->hw->max_rates = 1; in rt61pci_probe_hw_mode()
2690 rt2x00dev->hw->max_report_rates = 7; in rt61pci_probe_hw_mode()
2691 rt2x00dev->hw->max_rate_tries = 1; in rt61pci_probe_hw_mode()
2699 if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) { in rt61pci_probe_hw_mode()
2707 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) { in rt61pci_probe_hw_mode()
2721 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); in rt61pci_probe_hw_mode()
2728 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); in rt61pci_probe_hw_mode()
2739 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) in rt61pci_probe_hw() argument
2747 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); in rt61pci_probe_hw()
2752 retval = rt61pci_validate_eeprom(rt2x00dev); in rt61pci_probe_hw()
2756 retval = rt61pci_init_eeprom(rt2x00dev); in rt61pci_probe_hw()
2764 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_probe_hw()
2766 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_probe_hw()
2771 retval = rt61pci_probe_hw_mode(rt2x00dev); in rt61pci_probe_hw()
2779 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2784 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2785 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2787 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2788 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2793 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt61pci_probe_hw()
2806 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_conf_tx() local
2830 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); in rt61pci_conf_tx()
2837 reg = rt2x00mmio_register_read(rt2x00dev, offset); in rt61pci_conf_tx()
2839 rt2x00mmio_register_write(rt2x00dev, offset, reg); in rt61pci_conf_tx()
2845 reg = rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR); in rt61pci_conf_tx()
2847 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); in rt61pci_conf_tx()
2849 reg = rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR); in rt61pci_conf_tx()
2851 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); in rt61pci_conf_tx()
2853 reg = rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR); in rt61pci_conf_tx()
2855 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); in rt61pci_conf_tx()
2862 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_get_tsf() local
2866 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13); in rt61pci_get_tsf()
2868 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12); in rt61pci_get_tsf()