Lines Matching +full:cmd +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
10 #include <linux/crc-itu-t.h>
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
52 } gpios; member
163 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_parse_gpios()
164 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_parse_gpios()
165 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_parse_gpios() local
168 gpios->enable = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
171 if (gpios->enable) { in wilc_parse_gpios()
173 gpios->reset = devm_gpiod_get(&spi->dev, in wilc_parse_gpios()
175 if (IS_ERR(gpios->reset)) { in wilc_parse_gpios()
176 dev_err(&spi->dev, "missing reset gpio.\n"); in wilc_parse_gpios()
177 return PTR_ERR(gpios->reset); in wilc_parse_gpios()
180 gpios->reset = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
188 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_wlan_power()
189 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_wlan_power() local
193 gpiod_set_value(gpios->enable, 1); in wilc_wlan_power()
196 gpiod_set_value(gpios->reset, 0); in wilc_wlan_power()
199 gpiod_set_value(gpios->reset, 1); in wilc_wlan_power()
201 gpiod_set_value(gpios->enable, 0); in wilc_wlan_power()
213 return -ENOMEM; in wilc_bus_probe()
215 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); in wilc_bus_probe()
220 wilc->dev = &spi->dev; in wilc_bus_probe()
221 wilc->bus_data = spi_priv; in wilc_bus_probe()
222 wilc->dev_irq_num = spi->irq; in wilc_bus_probe()
228 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); in wilc_bus_probe()
229 if (IS_ERR(wilc->rtc_clk)) { in wilc_bus_probe()
230 ret = PTR_ERR(wilc->rtc_clk); in wilc_bus_probe()
233 clk_prepare_enable(wilc->rtc_clk); in wilc_bus_probe()
247 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_bus_remove()
249 clk_disable_unprepare(wilc->rtc_clk); in wilc_bus_remove()
280 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx()
296 return -ENOMEM; in wilc_spi_tx()
299 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); in wilc_spi_tx()
308 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx()
312 dev_err(&spi->dev, in wilc_spi_tx()
315 ret = -EINVAL; in wilc_spi_tx()
323 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_rx()
340 return -ENOMEM; in wilc_spi_rx()
351 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_rx()
354 dev_err(&spi->dev, in wilc_spi_rx()
357 ret = -EINVAL; in wilc_spi_rx()
365 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx_rx()
389 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx_rx()
391 dev_err(&spi->dev, in wilc_spi_tx_rx()
394 ret = -EINVAL; in wilc_spi_tx_rx()
402 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_write()
403 struct wilc_spi *spi_priv = wilc->bus_data; in spi_data_write()
406 u8 cmd, order, crc[2]; in spi_data_write() local
428 cmd = 0xf0; in spi_data_write()
429 cmd |= order; in spi_data_write()
431 if (wilc_spi_tx(wilc, &cmd, 1)) { in spi_data_write()
432 dev_err(&spi->dev, in spi_data_write()
433 "Failed data block cmd write, bus error...\n"); in spi_data_write()
434 result = -EINVAL; in spi_data_write()
442 dev_err(&spi->dev, in spi_data_write()
444 result = -EINVAL; in spi_data_write()
451 if (spi_priv->crc16_enabled) { in spi_data_write()
456 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); in spi_data_write()
457 result = -EINVAL; in spi_data_write()
466 sz -= nbytes; in spi_data_write()
482 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, in wilc_spi_single_read() argument
485 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_single_read()
486 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_single_read()
497 c->cmd_type = cmd; in wilc_spi_single_read()
498 if (cmd == CMD_SINGLE_READ) { in wilc_spi_single_read()
499 c->u.simple_cmd.addr[0] = adr >> 16; in wilc_spi_single_read()
500 c->u.simple_cmd.addr[1] = adr >> 8; in wilc_spi_single_read()
501 c->u.simple_cmd.addr[2] = adr; in wilc_spi_single_read()
502 } else if (cmd == CMD_INTERNAL_READ) { in wilc_spi_single_read()
503 c->u.simple_cmd.addr[0] = adr >> 8; in wilc_spi_single_read()
505 c->u.simple_cmd.addr[0] |= BIT(7); in wilc_spi_single_read()
506 c->u.simple_cmd.addr[1] = adr; in wilc_spi_single_read()
507 c->u.simple_cmd.addr[2] = 0x0; in wilc_spi_single_read()
509 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); in wilc_spi_single_read()
510 return -EINVAL; in wilc_spi_single_read()
516 if (spi_priv->crc7_enabled) { in wilc_spi_single_read()
517 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_single_read()
523 dev_err(&spi->dev, in wilc_spi_single_read()
526 return -EINVAL; in wilc_spi_single_read()
530 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_single_read()
531 return -EINVAL; in wilc_spi_single_read()
535 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_single_read()
536 if (!spi_priv->probing_crc) in wilc_spi_single_read()
537 dev_err(&spi->dev, in wilc_spi_single_read()
538 "Failed cmd, cmd (%02x), resp (%02x)\n", in wilc_spi_single_read()
539 cmd, r->rsp_cmd_type); in wilc_spi_single_read()
540 return -EINVAL; in wilc_spi_single_read()
543 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_single_read()
544 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_single_read()
545 r->status); in wilc_spi_single_read()
546 return -EINVAL; in wilc_spi_single_read()
550 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) in wilc_spi_single_read()
554 dev_err(&spi->dev, "Error, data start missing\n"); in wilc_spi_single_read()
555 return -EINVAL; in wilc_spi_single_read()
558 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; in wilc_spi_single_read()
561 memcpy(b, r_data->data, 4); in wilc_spi_single_read()
563 if (!clockless && spi_priv->crc16_enabled) { in wilc_spi_single_read()
564 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; in wilc_spi_single_read()
565 crc_calc = crc_itu_t(0xffff, r_data->data, 4); in wilc_spi_single_read()
567 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_single_read()
570 return -EINVAL; in wilc_spi_single_read()
577 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, in wilc_spi_write_cmd() argument
580 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_cmd()
581 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_write_cmd()
590 c->cmd_type = cmd; in wilc_spi_write_cmd()
591 if (cmd == CMD_INTERNAL_WRITE) { in wilc_spi_write_cmd()
592 c->u.internal_w_cmd.addr[0] = adr >> 8; in wilc_spi_write_cmd()
594 c->u.internal_w_cmd.addr[0] |= BIT(7); in wilc_spi_write_cmd()
596 c->u.internal_w_cmd.addr[1] = adr; in wilc_spi_write_cmd()
597 c->u.internal_w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
599 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
600 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
601 } else if (cmd == CMD_SINGLE_WRITE) { in wilc_spi_write_cmd()
602 c->u.w_cmd.addr[0] = adr >> 16; in wilc_spi_write_cmd()
603 c->u.w_cmd.addr[1] = adr >> 8; in wilc_spi_write_cmd()
604 c->u.w_cmd.addr[2] = adr; in wilc_spi_write_cmd()
605 c->u.w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
607 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
608 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
610 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); in wilc_spi_write_cmd()
611 return -EINVAL; in wilc_spi_write_cmd()
614 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
620 dev_err(&spi->dev, in wilc_spi_write_cmd()
623 return -EINVAL; in wilc_spi_write_cmd()
627 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_write_cmd()
628 return -EINVAL; in wilc_spi_write_cmd()
636 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_write_cmd()
637 dev_err(&spi->dev, in wilc_spi_write_cmd()
638 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_write_cmd()
639 cmd, r->rsp_cmd_type); in wilc_spi_write_cmd()
640 return -EINVAL; in wilc_spi_write_cmd()
643 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_write_cmd()
644 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_write_cmd()
645 r->status); in wilc_spi_write_cmd()
646 return -EINVAL; in wilc_spi_write_cmd()
652 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) in wilc_spi_dma_rw() argument
654 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_dma_rw()
655 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_dma_rw()
667 c->cmd_type = cmd; in wilc_spi_dma_rw()
668 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { in wilc_spi_dma_rw()
669 c->u.dma_cmd.addr[0] = adr >> 16; in wilc_spi_dma_rw()
670 c->u.dma_cmd.addr[1] = adr >> 8; in wilc_spi_dma_rw()
671 c->u.dma_cmd.addr[2] = adr; in wilc_spi_dma_rw()
672 c->u.dma_cmd.size[0] = sz >> 8; in wilc_spi_dma_rw()
673 c->u.dma_cmd.size[1] = sz; in wilc_spi_dma_rw()
675 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
676 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
677 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { in wilc_spi_dma_rw()
678 c->u.dma_cmd_ext.addr[0] = adr >> 16; in wilc_spi_dma_rw()
679 c->u.dma_cmd_ext.addr[1] = adr >> 8; in wilc_spi_dma_rw()
680 c->u.dma_cmd_ext.addr[2] = adr; in wilc_spi_dma_rw()
681 c->u.dma_cmd_ext.size[0] = sz >> 16; in wilc_spi_dma_rw()
682 c->u.dma_cmd_ext.size[1] = sz >> 8; in wilc_spi_dma_rw()
683 c->u.dma_cmd_ext.size[2] = sz; in wilc_spi_dma_rw()
685 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
686 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
688 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", in wilc_spi_dma_rw()
689 cmd); in wilc_spi_dma_rw()
690 return -EINVAL; in wilc_spi_dma_rw()
692 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
698 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", in wilc_spi_dma_rw()
700 return -EINVAL; in wilc_spi_dma_rw()
704 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_dma_rw()
705 return -EINVAL; in wilc_spi_dma_rw()
709 if (r->rsp_cmd_type != cmd) { in wilc_spi_dma_rw()
710 dev_err(&spi->dev, in wilc_spi_dma_rw()
711 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_dma_rw()
712 cmd, r->rsp_cmd_type); in wilc_spi_dma_rw()
713 return -EINVAL; in wilc_spi_dma_rw()
716 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_dma_rw()
717 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_dma_rw()
718 r->status); in wilc_spi_dma_rw()
719 return -EINVAL; in wilc_spi_dma_rw()
722 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) in wilc_spi_dma_rw()
737 dev_err(&spi->dev, in wilc_spi_dma_rw()
739 return -EINVAL; in wilc_spi_dma_rw()
743 } while (retry--); in wilc_spi_dma_rw()
749 dev_err(&spi->dev, in wilc_spi_dma_rw()
751 return -EINVAL; in wilc_spi_dma_rw()
757 if (spi_priv->crc16_enabled) { in wilc_spi_dma_rw()
759 dev_err(&spi->dev, in wilc_spi_dma_rw()
761 return -EINVAL; in wilc_spi_dma_rw()
766 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_dma_rw()
769 return -EINVAL; in wilc_spi_dma_rw()
774 sz -= nbytes; in wilc_spi_dma_rw()
779 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) in wilc_spi_special_cmd() argument
781 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_special_cmd()
782 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_special_cmd()
788 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) in wilc_spi_special_cmd()
789 return -EINVAL; in wilc_spi_special_cmd()
794 c->cmd_type = cmd; in wilc_spi_special_cmd()
796 if (cmd == CMD_RESET) in wilc_spi_special_cmd()
797 memset(c->u.simple_cmd.addr, 0xFF, 3); in wilc_spi_special_cmd()
802 if (spi_priv->crc7_enabled) { in wilc_spi_special_cmd()
803 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_special_cmd()
807 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", in wilc_spi_special_cmd()
809 return -EINVAL; in wilc_spi_special_cmd()
813 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_special_cmd()
814 return -EINVAL; in wilc_spi_special_cmd()
818 if (r->rsp_cmd_type != cmd) { in wilc_spi_special_cmd()
819 if (!spi_priv->probing_crc) in wilc_spi_special_cmd()
820 dev_err(&spi->dev, in wilc_spi_special_cmd()
821 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_special_cmd()
822 cmd, r->rsp_cmd_type); in wilc_spi_special_cmd()
823 return -EINVAL; in wilc_spi_special_cmd()
826 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_special_cmd()
827 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_special_cmd()
828 r->status); in wilc_spi_special_cmd()
829 return -EINVAL; in wilc_spi_special_cmd()
836 struct spi_device *spi = to_spi_device(wl->dev); in wilc_spi_reset_cmd_sequence()
837 struct wilc_spi *spi_priv = wl->bus_data; in wilc_spi_reset_cmd_sequence()
839 if (!spi_priv->probing_crc) in wilc_spi_reset_cmd_sequence()
840 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr); in wilc_spi_reset_cmd_sequence()
849 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read_reg()
851 u8 cmd = CMD_SINGLE_READ; in wilc_spi_read_reg() local
857 cmd = CMD_INTERNAL_READ; in wilc_spi_read_reg()
862 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); in wilc_spi_read_reg()
872 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); in wilc_spi_read_reg()
881 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read()
886 return -EINVAL; in wilc_spi_read()
894 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); in wilc_spi_read()
904 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_write()
913 dev_err(&spi->dev, "Failed internal write cmd...\n"); in spi_internal_write()
923 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_read()
924 struct wilc_spi *spi_priv = wilc->bus_data; in spi_internal_read()
935 if (!spi_priv->probing_crc) in spi_internal_read()
936 dev_err(&spi->dev, "Failed internal read cmd...\n"); in spi_internal_read()
952 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_reg()
954 u8 cmd = CMD_SINGLE_WRITE; in wilc_spi_write_reg() local
960 cmd = CMD_INTERNAL_WRITE; in wilc_spi_write_reg()
965 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); in wilc_spi_write_reg()
969 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); in wilc_spi_write_reg()
979 static int spi_data_rsp(struct wilc *wilc, u8 cmd) in spi_data_rsp() argument
981 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_rsp()
991 * second-to-last packet before the one for the final packet. in spi_data_rsp()
999 dev_err(&spi->dev, "Failed bus error...\n"); in spi_data_rsp()
1003 for (i = sizeof(rsp) - 2; i >= 0; --i) in spi_data_rsp()
1008 dev_err(&spi->dev, in spi_data_rsp()
1011 return -1; in spi_data_rsp()
1018 dev_err(&spi->dev, "Data response error (%02x %02x)\n", in spi_data_rsp()
1020 return -1; in spi_data_rsp()
1027 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write()
1035 return -EINVAL; in wilc_spi_write()
1041 dev_err(&spi->dev, in wilc_spi_write()
1042 "Failed cmd, write block (%08x)...\n", addr); in wilc_spi_write()
1052 dev_err(&spi->dev, "Failed block data write...\n"); in wilc_spi_write()
1062 dev_err(&spi->dev, "Failed block data rsp...\n"); in wilc_spi_write()
1079 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_reset()
1080 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_reset()
1084 if (result && !spi_priv->probing_crc) in wilc_spi_reset()
1085 dev_err(&spi->dev, "Failed cmd reset\n"); in wilc_spi_reset()
1092 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_is_init()
1094 return spi_priv->isinit; in wilc_spi_is_init()
1099 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_deinit()
1101 spi_priv->isinit = false; in wilc_spi_deinit()
1108 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_init()
1109 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_init()
1114 if (spi_priv->isinit) { in wilc_spi_init()
1120 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_spi_init()
1134 spi_priv->probing_crc = true; in wilc_spi_init()
1135 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_init()
1136 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ in wilc_spi_init()
1141 spi_priv->crc7_enabled = !enable_crc7; in wilc_spi_init()
1144 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); in wilc_spi_init()
1160 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); in wilc_spi_init()
1165 dev_err(&spi->dev, in wilc_spi_init()
1171 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_init()
1172 spi_priv->crc16_enabled = enable_crc16; in wilc_spi_init()
1174 /* re-read to make sure new settings are in effect: */ in wilc_spi_init()
1177 spi_priv->probing_crc = false; in wilc_spi_init()
1184 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_spi_init()
1188 spi_priv->isinit = true; in wilc_spi_init()
1198 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); in wilc_spi_read_size()
1206 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, in wilc_spi_read_int()
1218 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1224 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1229 retry--; in wilc_spi_clear_int_ext()
1236 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_sync_ext()
1241 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); in wilc_spi_sync_ext()
1242 return -EINVAL; in wilc_spi_sync_ext()
1250 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1257 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1267 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1272 for (i = 0; (i < 5) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1277 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1284 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1289 for (i = 0; (i < 3) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1294 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()