Lines Matching refs:dev
9 static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev) in mt76x2u_mac_fixup_xtal() argument
14 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); in mt76x2u_mac_fixup_xtal()
24 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); in mt76x2u_mac_fixup_xtal()
32 mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5), in mt76x2u_mac_fixup_xtal()
34 mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL); in mt76x2u_mac_fixup_xtal()
36 mt76_wr(dev, 0x504, 0x06000000); in mt76x2u_mac_fixup_xtal()
37 mt76_wr(dev, 0x50c, 0x08800000); in mt76x2u_mac_fixup_xtal()
39 mt76_wr(dev, 0x504, 0x0); in mt76x2u_mac_fixup_xtal()
42 mt76_rmw_field(dev, MT_XIFS_TIME_CFG, in mt76x2u_mac_fixup_xtal()
44 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, MT_BKOFF_SLOT_CFG_CC_DELAY, 1); in mt76x2u_mac_fixup_xtal()
47 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); in mt76x2u_mac_fixup_xtal()
49 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); in mt76x2u_mac_fixup_xtal()
52 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); in mt76x2u_mac_fixup_xtal()
55 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); in mt76x2u_mac_fixup_xtal()
62 int mt76x2u_mac_reset(struct mt76x02_dev *dev) in mt76x2u_mac_reset() argument
64 mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5)); in mt76x2u_mac_reset()
67 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); in mt76x2u_mac_reset()
68 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); in mt76x2u_mac_reset()
70 mt76_write_mac_initvals(dev); in mt76x2u_mac_reset()
72 mt76_wr(dev, MT_TX_LINK_CFG, 0x1020); in mt76x2u_mac_reset()
73 mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13); in mt76x2u_mac_reset()
74 mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00); in mt76x2u_mac_reset()
76 mt76_wr(dev, MT_WMM_AIFSN, 0x2273); in mt76x2u_mac_reset()
77 mt76_wr(dev, MT_WMM_CWMIN, 0x2344); in mt76x2u_mac_reset()
78 mt76_wr(dev, MT_WMM_CWMAX, 0x34aa); in mt76x2u_mac_reset()
80 mt76_clear(dev, MT_MAC_SYS_CTRL, in mt76x2u_mac_reset()
84 if (is_mt7612(dev)) in mt76x2u_mac_reset()
85 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); in mt76x2u_mac_reset()
87 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); in mt76x2u_mac_reset()
88 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); in mt76x2u_mac_reset()
90 mt76x2u_mac_fixup_xtal(dev); in mt76x2u_mac_reset()
95 int mt76x2u_mac_stop(struct mt76x02_dev *dev) in mt76x2u_mac_stop() argument
101 if (test_bit(MT76_REMOVED, &dev->mphy.state)) in mt76x2u_mac_stop()
104 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG); in mt76x2u_mac_stop()
105 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT); in mt76x2u_mac_stop()
107 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); in mt76x2u_mac_stop()
108 mt76_clear(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); in mt76x2u_mac_stop()
112 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); in mt76x2u_mac_stop()
120 if (!(mt76_rr(dev, 0x0438) & 0xffffffff) && in mt76x2u_mac_stop()
121 !(mt76_rr(dev, 0x0a30) & 0x000000ff) && in mt76x2u_mac_stop()
122 !(mt76_rr(dev, 0x0a34) & 0xff00ff00)) in mt76x2u_mac_stop()
128 mt76_clear(dev, MT_MAC_SYS_CTRL, in mt76x2u_mac_stop()
134 if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) && in mt76x2u_mac_stop()
135 !mt76_rr(dev, MT_BBP(IBI, 12))) { in mt76x2u_mac_stop()
143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
152 if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) && in mt76x2u_mac_stop()
153 !(mt76_rr(dev, 0x0a30) & 0xffffffff) && in mt76x2u_mac_stop()
154 !(mt76_rr(dev, 0x0a34) & 0xffffffff) && in mt76x2u_mac_stop()
160 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 2000)) in mt76x2u_mac_stop()
161 dev_warn(dev->mt76.dev, "MAC RX failed to stop\n"); in mt76x2u_mac_stop()
165 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); in mt76x2u_mac_stop()
171 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg); in mt76x2u_mac_stop()