12 	struct mt76x02_dev *dev = hw->priv;  in mt76x2_start()  local
14 	mt76x02_mac_start(dev);  in mt76x2_start()
15 	mt76x2_phy_start(dev);  in mt76x2_start()
17 	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,  in mt76x2_start()
19 	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,  in mt76x2_start()
22 	set_bit(MT76_STATE_RUNNING, &dev->mphy.state);  in mt76x2_start()
29 	struct mt76x02_dev *dev = hw->priv;  in mt76x2_stop()  local
31 	clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);  in mt76x2_stop()
32 	mt76x2_stop_hardware(dev);  in mt76x2_stop()
36 mt76x2_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef)  in mt76x2_set_channel()  argument
38 	cancel_delayed_work_sync(&dev->cal_work);  in mt76x2_set_channel()
39 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);  in mt76x2_set_channel()
40 	tasklet_disable(&dev->dfs_pd.dfs_tasklet);  in mt76x2_set_channel()
42 	mutex_lock(&dev->mt76.mutex);  in mt76x2_set_channel()
43 	set_bit(MT76_RESET, &dev->mphy.state);  in mt76x2_set_channel()
45 	mt76_set_channel(&dev->mphy);  in mt76x2_set_channel()
47 	mt76x2_mac_stop(dev, true);  in mt76x2_set_channel()
48 	mt76x2_phy_set_channel(dev, chandef);  in mt76x2_set_channel()
50 	mt76x02_mac_cc_reset(dev);  in mt76x2_set_channel()
51 	mt76x02_dfs_init_params(dev);  in mt76x2_set_channel()
53 	mt76x2_mac_resume(dev);  in mt76x2_set_channel()
55 	clear_bit(MT76_RESET, &dev->mphy.state);  in mt76x2_set_channel()
56 	mutex_unlock(&dev->mt76.mutex);  in mt76x2_set_channel()
58 	tasklet_enable(&dev->dfs_pd.dfs_tasklet);  in mt76x2_set_channel()
59 	tasklet_enable(&dev->mt76.pre_tbtt_tasklet);  in mt76x2_set_channel()
61 	mt76_txq_schedule_all(&dev->mphy);  in mt76x2_set_channel()
67 	struct mt76x02_dev *dev = hw->priv;  in mt76x2_config()  local
69 	mutex_lock(&dev->mt76.mutex);  in mt76x2_config()
73 			dev->mt76.rxfilter |= MT_RX_FILTR_CFG_PROMISC;  in mt76x2_config()
75 			dev->mt76.rxfilter &= ~MT_RX_FILTR_CFG_PROMISC;  in mt76x2_config()
77 		mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);  in mt76x2_config()
81 		struct mt76_phy *mphy = &dev->mphy;  in mt76x2_config()
83 		dev->txpower_conf = hw->conf.power_level * 2;  in mt76x2_config()
84 		dev->txpower_conf = mt76_get_sar_power(mphy,  in mt76x2_config()
86 						       dev->txpower_conf);  in mt76x2_config()
88 		dev->txpower_conf -= 6;  in mt76x2_config()
90 		if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) {  in mt76x2_config()
91 			mt76x2_phy_set_txpower(dev);  in mt76x2_config()
92 			mt76x02_tx_set_txpwr_auto(dev, dev->txpower_conf);  in mt76x2_config()
96 	mutex_unlock(&dev->mt76.mutex);  in mt76x2_config()
100 		mt76x2_set_channel(dev, &hw->conf.chandef);  in mt76x2_config()
116 	struct mt76x02_dev *dev = hw->priv;  in mt76x2_set_antenna()  local
121 	mutex_lock(&dev->mt76.mutex);  in mt76x2_set_antenna()
123 	dev->mphy.chainmask = (tx_ant == 3) ? 0x202 : 0x101;  in mt76x2_set_antenna()
124 	dev->mphy.antenna_mask = tx_ant;  in mt76x2_set_antenna()
126 	mt76_set_stream_caps(&dev->mphy, true);  in mt76x2_set_antenna()
127 	mt76x2_phy_set_antenna(dev);  in mt76x2_set_antenna()
129 	mutex_unlock(&dev->mt76.mutex);  in mt76x2_set_antenna()