Lines Matching refs:dev
13 mt76x2_mac_pbf_init(struct mt76x02_dev *dev) in mt76x2_mac_pbf_init() argument
23 mt76_set(dev, MT_PBF_SYS_CTRL, val); in mt76x2_mac_pbf_init()
24 mt76_clear(dev, MT_PBF_SYS_CTRL, val); in mt76x2_mac_pbf_init()
26 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); in mt76x2_mac_pbf_init()
27 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); in mt76x2_mac_pbf_init()
31 mt76x2_fixup_xtal(struct mt76x02_dev *dev) in mt76x2_fixup_xtal() argument
36 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); in mt76x2_fixup_xtal()
46 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); in mt76x2_fixup_xtal()
54 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset); in mt76x2_fixup_xtal()
55 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); in mt76x2_fixup_xtal()
57 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); in mt76x2_fixup_xtal()
60 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); in mt76x2_fixup_xtal()
63 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); in mt76x2_fixup_xtal()
70 int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard) in mt76x2_mac_reset() argument
72 const u8 *macaddr = dev->mphy.macaddr; in mt76x2_mac_reset()
76 if (!mt76x02_wait_for_mac(&dev->mt76)) in mt76x2_mac_reset()
79 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); in mt76x2_mac_reset()
88 mt76_wr(dev, MT_WPDMA_GLO_CFG, val); in mt76x2_mac_reset()
90 mt76x2_mac_pbf_init(dev); in mt76x2_mac_reset()
91 mt76_write_mac_initvals(dev); in mt76x2_mac_reset()
92 mt76x2_fixup_xtal(dev); in mt76x2_mac_reset()
94 mt76_clear(dev, MT_MAC_SYS_CTRL, in mt76x2_mac_reset()
98 if (is_mt7612(dev)) in mt76x2_mac_reset()
99 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); in mt76x2_mac_reset()
101 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); in mt76x2_mac_reset()
102 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); in mt76x2_mac_reset()
104 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); in mt76x2_mac_reset()
105 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); in mt76x2_mac_reset()
107 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); in mt76x2_mac_reset()
109 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); in mt76x2_mac_reset()
110 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); in mt76x2_mac_reset()
112 mt76x02_mac_setaddr(dev, macaddr); in mt76x2_mac_reset()
113 mt76x02e_init_beacon_config(dev); in mt76x2_mac_reset()
118 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); in mt76x2_mac_reset()
121 mt76x02_mac_wcid_setup(dev, i, 0, NULL); in mt76x2_mac_reset()
122 mt76_wr(dev, MT_WCID_TX_RATE(i), 0); in mt76x2_mac_reset()
123 mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0); in mt76x2_mac_reset()
127 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL); in mt76x2_mac_reset()
131 mt76x02_mac_shared_key_setup(dev, i, k, NULL); in mt76x2_mac_reset()
134 mt76_rr(dev, MT_TX_STAT_FIFO); in mt76x2_mac_reset()
136 mt76x02_set_tx_ackto(dev); in mt76x2_mac_reset()
142 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev) in mt76x2_power_on_rf_patch() argument
144 mt76_set(dev, 0x10130, BIT(0) | BIT(16)); in mt76x2_power_on_rf_patch()
147 mt76_clear(dev, 0x1001c, 0xff); in mt76x2_power_on_rf_patch()
148 mt76_set(dev, 0x1001c, 0x30); in mt76x2_power_on_rf_patch()
150 mt76_wr(dev, 0x10014, 0x484f); in mt76x2_power_on_rf_patch()
153 mt76_set(dev, 0x10130, BIT(17)); in mt76x2_power_on_rf_patch()
156 mt76_clear(dev, 0x10130, BIT(16)); in mt76x2_power_on_rf_patch()
159 mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); in mt76x2_power_on_rf_patch()
163 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit) in mt76x2_power_on_rf() argument
168 mt76_set(dev, 0x10130, BIT(0) << shift); in mt76x2_power_on_rf()
172 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift); in mt76x2_power_on_rf()
176 mt76_clear(dev, 0x10130, BIT(2) << shift); in mt76x2_power_on_rf()
179 mt76x2_power_on_rf_patch(dev); in mt76x2_power_on_rf()
181 mt76_set(dev, 0x530, 0xf); in mt76x2_power_on_rf()
185 mt76x2_power_on(struct mt76x02_dev *dev) in mt76x2_power_on() argument
190 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP); in mt76x2_power_on()
196 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000); in mt76x2_power_on()
198 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16); in mt76x2_power_on()
201 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24); in mt76x2_power_on()
204 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24); in mt76x2_power_on()
205 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff); in mt76x2_power_on()
208 mt76_clear(dev, 0x11204, BIT(3)); in mt76x2_power_on()
211 mt76_set(dev, 0x10080, BIT(0)); in mt76x2_power_on()
214 mt76_clear(dev, 0x10064, BIT(18)); in mt76x2_power_on()
216 mt76x2_power_on_rf(dev, 0); in mt76x2_power_on()
217 mt76x2_power_on_rf(dev, 1); in mt76x2_power_on()
220 int mt76x2_resume_device(struct mt76x02_dev *dev) in mt76x2_resume_device() argument
224 mt76x02_dma_disable(dev); in mt76x2_resume_device()
225 mt76x2_reset_wlan(dev, true); in mt76x2_resume_device()
226 mt76x2_power_on(dev); in mt76x2_resume_device()
228 err = mt76x2_mac_reset(dev, true); in mt76x2_resume_device()
232 mt76x02_mac_start(dev); in mt76x2_resume_device()
234 return mt76x2_mcu_init(dev); in mt76x2_resume_device()
237 static int mt76x2_init_hardware(struct mt76x02_dev *dev) in mt76x2_init_hardware() argument
241 mt76x02_dma_disable(dev); in mt76x2_init_hardware()
242 mt76x2_reset_wlan(dev, true); in mt76x2_init_hardware()
243 mt76x2_power_on(dev); in mt76x2_init_hardware()
245 ret = mt76x2_eeprom_init(dev); in mt76x2_init_hardware()
249 ret = mt76x2_mac_reset(dev, true); in mt76x2_init_hardware()
253 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); in mt76x2_init_hardware()
255 ret = mt76x02_dma_init(dev); in mt76x2_init_hardware()
259 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); in mt76x2_init_hardware()
260 mt76x02_mac_start(dev); in mt76x2_init_hardware()
262 ret = mt76x2_mcu_init(dev); in mt76x2_init_hardware()
266 mt76x2_mac_stop(dev, false); in mt76x2_init_hardware()
271 void mt76x2_stop_hardware(struct mt76x02_dev *dev) in mt76x2_stop_hardware() argument
273 cancel_delayed_work_sync(&dev->cal_work); in mt76x2_stop_hardware()
274 cancel_delayed_work_sync(&dev->mphy.mac_work); in mt76x2_stop_hardware()
275 cancel_delayed_work_sync(&dev->wdt_work); in mt76x2_stop_hardware()
276 clear_bit(MT76_RESTART, &dev->mphy.state); in mt76x2_stop_hardware()
277 mt76x02_mcu_set_radio_state(dev, false); in mt76x2_stop_hardware()
278 mt76x2_mac_stop(dev, false); in mt76x2_stop_hardware()
281 void mt76x2_cleanup(struct mt76x02_dev *dev) in mt76x2_cleanup() argument
283 tasklet_disable(&dev->dfs_pd.dfs_tasklet); in mt76x2_cleanup()
284 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); in mt76x2_cleanup()
285 mt76x2_stop_hardware(dev); in mt76x2_cleanup()
286 mt76_dma_cleanup(&dev->mt76); in mt76x2_cleanup()
287 mt76x02_mcu_cleanup(dev); in mt76x2_cleanup()
290 int mt76x2_register_device(struct mt76x02_dev *dev) in mt76x2_register_device() argument
294 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate); in mt76x2_register_device()
295 ret = mt76x02_init_device(dev); in mt76x2_register_device()
299 ret = mt76x2_init_hardware(dev); in mt76x2_register_device()
303 mt76x02_config_mac_addr_list(dev); in mt76x2_register_device()
305 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, in mt76x2_register_device()
310 mt76x02_init_debugfs(dev); in mt76x2_register_device()
311 mt76x2_init_txpower(dev, &dev->mphy.sband_2g.sband); in mt76x2_register_device()
312 mt76x2_init_txpower(dev, &dev->mphy.sband_5g.sband); in mt76x2_register_device()
317 mt76x2_stop_hardware(dev); in mt76x2_register_device()