12 void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev)  in mt76x02_phy_set_rxpath()  argument
16 	val = mt76_rr(dev, MT_BBP(AGC, 0));  in mt76x02_phy_set_rxpath()
19 	switch (dev->mphy.chainmask & 0xf) {  in mt76x02_phy_set_rxpath()
28 	mt76_wr(dev, MT_BBP(AGC, 0), val);  in mt76x02_phy_set_rxpath()
30 	val = mt76_rr(dev, MT_BBP(AGC, 0));  in mt76x02_phy_set_rxpath()
34 void mt76x02_phy_set_txdac(struct mt76x02_dev *dev)  in mt76x02_phy_set_txdac()  argument
38 	txpath = (dev->mphy.chainmask >> 8) & 0xf;  in mt76x02_phy_set_txdac()
41 		mt76_set(dev, MT_BBP(TXBE, 5), 0x3);  in mt76x02_phy_set_txdac()
44 		mt76_clear(dev, MT_BBP(TXBE, 5), 0x3);  in mt76x02_phy_set_txdac()
93 void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1)  in mt76x02_phy_set_txpower()  argument
95 	struct mt76x02_rate_power *t = &dev->rate_power;  in mt76x02_phy_set_txpower()
97 	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);  in mt76x02_phy_set_txpower()
98 	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);  in mt76x02_phy_set_txpower()
100 	mt76_wr(dev, MT_TX_PWR_CFG_0,  in mt76x02_phy_set_txpower()
103 	mt76_wr(dev, MT_TX_PWR_CFG_1,  in mt76x02_phy_set_txpower()
106 	mt76_wr(dev, MT_TX_PWR_CFG_2,  in mt76x02_phy_set_txpower()
109 	mt76_wr(dev, MT_TX_PWR_CFG_3,  in mt76x02_phy_set_txpower()
112 	mt76_wr(dev, MT_TX_PWR_CFG_4,  in mt76x02_phy_set_txpower()
114 	mt76_wr(dev, MT_TX_PWR_CFG_7,  in mt76x02_phy_set_txpower()
117 	mt76_wr(dev, MT_TX_PWR_CFG_8,  in mt76x02_phy_set_txpower()
119 	mt76_wr(dev, MT_TX_PWR_CFG_9,  in mt76x02_phy_set_txpower()
124 void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl)  in mt76x02_phy_set_bw()  argument
143 	mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);  in mt76x02_phy_set_bw()
144 	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);  in mt76x02_phy_set_bw()
145 	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);  in mt76x02_phy_set_bw()
146 	mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);  in mt76x02_phy_set_bw()
150 void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,  in mt76x02_phy_set_band()  argument
155 		mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);  in mt76x02_phy_set_band()
156 		mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);  in mt76x02_phy_set_band()
159 		mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);  in mt76x02_phy_set_band()
160 		mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);  in mt76x02_phy_set_band()
164 	mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,  in mt76x02_phy_set_band()
169 bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev)  in mt76x02_phy_adjust_vga_gain()  argument
171 	u8 limit = dev->cal.low_gain > 0 ? 16 : 4;  in mt76x02_phy_adjust_vga_gain()
176 			      mt76_rr(dev, MT_RX_STAT_1));  in mt76x02_phy_adjust_vga_gain()
177 	dev->cal.false_cca = false_cca;  in mt76x02_phy_adjust_vga_gain()
178 	if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) {  in mt76x02_phy_adjust_vga_gain()
179 		dev->cal.agc_gain_adjust += 2;  in mt76x02_phy_adjust_vga_gain()
181 	} else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||  in mt76x02_phy_adjust_vga_gain()
182 		   (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) {  in mt76x02_phy_adjust_vga_gain()
183 		dev->cal.agc_gain_adjust -= 2;  in mt76x02_phy_adjust_vga_gain()
187 	dev->cal.agc_lowest_gain = dev->cal.agc_gain_adjust >= limit;  in mt76x02_phy_adjust_vga_gain()
193 void mt76x02_init_agc_gain(struct mt76x02_dev *dev)  in mt76x02_init_agc_gain()  argument
195 	dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8),  in mt76x02_init_agc_gain()
197 	dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9),  in mt76x02_init_agc_gain()
199 	memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,  in mt76x02_init_agc_gain()
200 	       sizeof(dev->cal.agc_gain_cur));  in mt76x02_init_agc_gain()
201 	dev->cal.low_gain = -1;  in mt76x02_init_agc_gain()
202 	dev->cal.gain_init_done = true;  in mt76x02_init_agc_gain()