18 	struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD];  in mt76x02_pre_tbtt_tasklet()
141 	mt76_txq_schedule_all(&dev->mphy);  in mt76x02_tx_worker()
154 		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);  in mt76x02_poll_tx()
161 		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);  in mt76x02_poll_tx()
193 		ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),  in mt76x02_dma_init()
200 	ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,  in mt76x02_dma_init()
260 	if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))  in mt76x02_irq_handler()
285 			mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]);  in mt76x02_irq_handler()
350 		q = dev->mphy.q_tx[i];  in mt76x02_tx_hang()
392 	clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);  in mt76x02_reset_state()
433 	set_bit(MT76_RESET, &dev->mphy.state);  in mt76x02_watchdog_reset()
472 		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);  in mt76x02_watchdog_reset()
494 	clear_bit(MT76_RESET, &dev->mphy.state);  in mt76x02_watchdog_reset()
510 		set_bit(MT76_RESTART, &dev->mphy.state);  in mt76x02_watchdog_reset()
515 		mt76_txq_schedule_all(&dev->mphy);  in mt76x02_watchdog_reset()
527 	clear_bit(MT76_RESTART, &dev->mphy.state);  in mt76x02_reconfig_complete()
533 	if (test_bit(MT76_RESTART, &dev->mphy.state))  in mt76x02_check_tx_hang()