Lines Matching refs:u32
21 mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value) in mt76x0_rf_csr_wr()
59 static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset) in mt76x0_rf_csr_rr()
62 u32 val; in mt76x0_rf_csr_rr()
103 mt76x0_rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val) in mt76x0_rf_wr()
119 static int mt76x0_rf_rr(struct mt76x02_dev *dev, u32 offset) in mt76x0_rf_rr()
122 u32 val; in mt76x0_rf_rr()
141 mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val) in mt76x0_rf_rmw()
156 mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val) in mt76x0_rf_set()
162 mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask) in mt76x0_rf_clear()
188 u32 val; in mt76x0_phy_wait_bbp_ready()
241 u32 mac_reg; in mt76x0_phy_set_chan_rf_params()
412 u32 val = pair->value; in mt76x0_phy_set_chan_bbp_params()
431 u32 wlan, coex3; in mt76x0_phy_ant_select()
506 u32 val; in mt76x0_phy_tssi_dc_calibrate()
547 u32 val; in mt76x0_phy_tssi_adc_calibrate()
579 u32 val, reg; in mt76x0_phy_get_rf_pa_mode()
669 u32 mantissa = val << 4; in mt76x0_phy_lin2db()
704 u32 data; in mt76x0_phy_get_delta_power()
865 u32 val, tx_alc, reg_val; in mt76x0_phy_calibrate()
916 u32 ext_cca_chan[4] = { in mt76x0_phy_set_channel()
941 u32 val; in mt76x0_phy_set_channel()
1122 u32 reg = rp[i].reg; in mt76x0_rf_patch_reg_array()